#include <pci.h>
#include <asm/io.h>
#include <dm/lists.h>
-#include <dm/root.h>
#include <dm/device-internal.h>
#if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
#include <asm/fsp/fsp_support.h>
/* Since buses may not be numbered yet try a little harder with bus 0 */
if (ret == -ENODEV) {
- ret = uclass_first_device(UCLASS_PCI, busp);
+ ret = uclass_first_device_err(UCLASS_PCI, busp);
if (ret)
return ret;
- else if (!*busp)
- return -ENODEV;
ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
}
return ops->write_config(bus, bdf, offset, value, size);
}
+int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
+ u32 clr, u32 set)
+{
+ ulong val;
+ int ret;
+
+ ret = pci_bus_read_config(bus, bdf, offset, &val, PCI_SIZE_32);
+ if (ret)
+ return ret;
+ val &= ~clr;
+ val |= set;
+
+ return pci_bus_write_config(bus, bdf, offset, val, PCI_SIZE_32);
+}
+
int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
enum pci_size_t size)
{
size);
}
-
int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
{
return pci_write_config(bdf, offset, value, PCI_SIZE_32);
return 0;
}
+int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set)
+{
+ u8 val;
+ int ret;
+
+ ret = dm_pci_read_config8(dev, offset, &val);
+ if (ret)
+ return ret;
+ val &= ~clr;
+ val |= set;
+
+ return dm_pci_write_config8(dev, offset, val);
+}
+
+int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set)
+{
+ u16 val;
+ int ret;
+
+ ret = dm_pci_read_config16(dev, offset, &val);
+ if (ret)
+ return ret;
+ val &= ~clr;
+ val |= set;
+
+ return dm_pci_write_config16(dev, offset, val);
+}
+
+int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set)
+{
+ u32 val;
+ int ret;
+
+ ret = dm_pci_read_config32(dev, offset, &val);
+ if (ret)
+ return ret;
+ val &= ~clr;
+ val |= set;
+
+ return dm_pci_write_config32(dev, offset, val);
+}
+
static void set_vga_bridge_bits(struct udevice *dev)
{
struct udevice *parent = dev->parent;
found_multi = false;
end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1,
PCI_MAX_PCI_FUNCTIONS - 1);
- for (bdf = PCI_BDF(bus->seq, 0, 0); bdf < end;
+ for (bdf = PCI_BDF(bus->seq, 0, 0); bdf <= end;
bdf += PCI_BDF(0, 0, 1)) {
struct pci_child_platdata *pplat;
struct udevice *dev;
return ret;
}
-static int pci_uclass_post_bind(struct udevice *bus)
-{
- /*
- * If there is no pci device listed in the device tree,
- * don't bother scanning the device tree.
- */
- if (bus->of_offset == -1)
- return 0;
-
- /*
- * Scan the device tree for devices. This does not probe the PCI bus,
- * as this is not permitted while binding. It just finds devices
- * mentioned in the device tree.
- *
- * Before relocation, only bind devices marked for pre-relocation
- * use.
- */
- return dm_scan_fdt_node(bus, gd->fdt_blob, bus->of_offset,
- gd->flags & GD_FLG_RELOC ? false : true);
-}
-
static int decode_regions(struct pci_controller *hose, const void *blob,
int parent_node, int node)
{
hose = bus->uclass_priv;
/* For bridges, use the top-level PCI controller */
- if (device_get_uclass_id(bus->parent) == UCLASS_ROOT) {
+ if (!device_is_on_pci_bus(bus)) {
hose->ctlr = bus;
ret = decode_regions(hose, gd->fdt_blob, bus->parent->of_offset,
bus->of_offset);
.id = UCLASS_PCI,
.name = "pci",
.flags = DM_UC_FLAG_SEQ_ALIAS,
- .post_bind = pci_uclass_post_bind,
+ .post_bind = dm_scan_fdt_dev,
.pre_probe = pci_uclass_pre_probe,
.post_probe = pci_uclass_post_probe,
.child_post_bind = pci_uclass_child_post_bind,
.id = UCLASS_PCI_GENERIC,
.of_match = pci_generic_ids,
};
+
+void pci_init(void)
+{
+ struct udevice *bus;
+
+ /*
+ * Enumerate all known controller devices. Enumeration has the side-
+ * effect of probing them, so PCIe devices will be enumerated too.
+ */
+ for (uclass_first_device(UCLASS_PCI, &bus);
+ bus;
+ uclass_next_device(&bus)) {
+ ;
+ }
+}