spi: omap3: pre-initialize bus-speed with max. slave-speed

[u-boot] / drivers / pci / pci-uclass.c

diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 504d7e3bb134d1422e901cda320c4a1a3b2df093..46e9c71bdfba5b729303ad3666ea9491bebfb59c 100644 (file)
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -1,19 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (c) 2014 Google, Inc
  * Written by Simon Glass <sjg@chromium.org>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
 #include <dm.h>
 #include <errno.h>
-#include <fdtdec.h>
 #include <inttypes.h>
 #include <pci.h>
 #include <asm/io.h>
-#include <dm/lists.h>
 #include <dm/device-internal.h>
+#include <dm/lists.h>
 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
 #include <asm/fsp/fsp_support.h>
 #endif
@@ -519,6 +517,64 @@ int pci_auto_config_devices(struct udevice *bus)
        return sub_bus;
 }
 
+int pci_generic_mmap_write_config(
+       struct udevice *bus,
+       int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
+       pci_dev_t bdf,
+       uint offset,
+       ulong value,
+       enum pci_size_t size)
+{
+       void *address;
+
+       if (addr_f(bus, bdf, offset, &address) < 0)
+               return 0;
+
+       switch (size) {
+       case PCI_SIZE_8:
+               writeb(value, address);
+               return 0;
+       case PCI_SIZE_16:
+               writew(value, address);
+               return 0;
+       case PCI_SIZE_32:
+               writel(value, address);
+               return 0;
+       default:
+               return -EINVAL;
+       }
+}
+
+int pci_generic_mmap_read_config(
+       struct udevice *bus,
+       int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
+       pci_dev_t bdf,
+       uint offset,
+       ulong *valuep,
+       enum pci_size_t size)
+{
+       void *address;
+
+       if (addr_f(bus, bdf, offset, &address) < 0) {
+               *valuep = pci_get_ff(size);
+               return 0;
+       }
+
+       switch (size) {
+       case PCI_SIZE_8:
+               *valuep = readb(address);
+               return 0;
+       case PCI_SIZE_16:
+               *valuep = readw(address);
+               return 0;
+       case PCI_SIZE_32:
+               *valuep = readl(address);
+               return 0;
+       default:
+               return -EINVAL;
+       }
+}
+
 int dm_pci_hose_probe_bus(struct udevice *bus)
 {
        int sub_bus;
@@ -754,22 +810,24 @@ error:
        return ret;
 }
 
-static int decode_regions(struct pci_controller *hose, const void *blob,
-                         int parent_node, int node)
+static void decode_regions(struct pci_controller *hose, ofnode parent_node,
+                          ofnode node)
 {
        int pci_addr_cells, addr_cells, size_cells;
-       phys_addr_t base = 0, size;
        int cells_per_record;
        const u32 *prop;
        int len;
        int i;
 
-       prop = fdt_getprop(blob, node, "ranges", &len);
-       if (!prop)
-               return -EINVAL;
-       pci_addr_cells = fdt_address_cells(blob, node);
-       addr_cells = fdt_address_cells(blob, parent_node);
-       size_cells = fdt_size_cells(blob, node);
+       prop = ofnode_get_property(node, "ranges", &len);
+       if (!prop) {
+               debug("%s: Cannot decode regions\n", __func__);
+               return;
+       }
+
+       pci_addr_cells = ofnode_read_simple_addr_cells(node);
+       addr_cells = ofnode_read_simple_addr_cells(parent_node);
+       size_cells = ofnode_read_simple_size_cells(node);
 
        /* PCI addresses are always 3-cells */
        len /= sizeof(u32);
@@ -805,6 +863,13 @@ static int decode_regions(struct pci_controller *hose, const void *blob,
                } else {
                        continue;
                }
+
+               if (!IS_ENABLED(CONFIG_SYS_PCI_64BIT) &&
+                   type == PCI_REGION_MEM && upper_32_bits(pci_addr)) {
+                       debug(" - beyond the 32-bit boundary, ignoring\n");
+                       continue;
+               }
+
                pos = -1;
                for (i = 0; i < hose->region_count; i++) {
                        if (hose->regions[i].flags == type)
@@ -817,22 +882,41 @@ static int decode_regions(struct pci_controller *hose, const void *blob,
        }
 
        /* Add a region for our local memory */
+#ifdef CONFIG_NR_DRAM_BANKS
+       bd_t *bd = gd->bd;
+
+       if (!bd)
+               return;
+
+       for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
+               if (bd->bi_dram[i].size) {
+                       pci_set_region(hose->regions + hose->region_count++,
+                                      bd->bi_dram[i].start,
+                                      bd->bi_dram[i].start,
+                                      bd->bi_dram[i].size,
+                                      PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+               }
+       }
+#else
+       phys_addr_t base = 0, size;
+
        size = gd->ram_size;
 #ifdef CONFIG_SYS_SDRAM_BASE
        base = CONFIG_SYS_SDRAM_BASE;
 #endif
        if (gd->pci_ram_top && gd->pci_ram_top < base + size)
                size = gd->pci_ram_top - base;
-       pci_set_region(hose->regions + hose->region_count++, base, base,
-                      size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+       if (size)
+               pci_set_region(hose->regions + hose->region_count++, base,
+                       base, size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+#endif
 
-       return 0;
+       return;
 }
 
 static int pci_uclass_pre_probe(struct udevice *bus)
 {
        struct pci_controller *hose;
-       int ret;
 
        debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name,
              bus->parent->name);
@@ -841,13 +925,7 @@ static int pci_uclass_pre_probe(struct udevice *bus)
        /* For bridges, use the top-level PCI controller */
        if (!device_is_on_pci_bus(bus)) {
                hose->ctlr = bus;
-               ret = decode_regions(hose, gd->fdt_blob,
-                                    dev_of_offset(bus->parent),
-                                    dev_of_offset(bus));
-               if (ret) {
-                       debug("%s: Cannot decode regions\n", __func__);
-                       return ret;
-               }
+               decode_regions(hose, dev_ofnode(bus->parent), dev_ofnode(bus));
        } else {
                struct pci_controller *parent_hose;
 
@@ -906,7 +984,7 @@ static int pci_uclass_child_post_bind(struct udevice *dev)
        struct fdt_pci_addr addr;
        int ret;
 
-       if (dev_of_offset(dev) == -1)
+       if (!dev_of_valid(dev))
                return 0;
 
        /*
@@ -914,8 +992,8 @@ static int pci_uclass_child_post_bind(struct udevice *dev)
         * just check the address.
         */
        pplat = dev_get_parent_platdata(dev);
-       ret = fdtdec_get_pci_addr(gd->fdt_blob, dev_of_offset(dev),
-                                 FDT_PCI_SPACE_CONFIG, "reg", &addr);
+       ret = ofnode_read_pci_addr(dev_ofnode(dev), FDT_PCI_SPACE_CONFIG, "reg",
+                                  &addr);
 
        if (ret) {
                if (ret != -ENOENT)
@@ -1104,6 +1182,11 @@ static int _dm_pci_bus_to_phys(struct udevice *ctlr,
        struct pci_region *res;
        int i;
 
+       if (hose->region_count == 0) {
+               *pa = bus_addr;
+               return 0;
+       }
+
        for (i = 0; i < hose->region_count; i++) {
                res = &hose->regions[i];
 
@@ -1167,6 +1250,11 @@ int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
        ctlr = pci_get_controller(dev);
        hose = dev_get_uclass_priv(ctlr);
 
+       if (hose->region_count == 0) {
+               *ba = phys_addr;
+               return 0;
+       }
+
        for (i = 0; i < hose->region_count; i++) {
                res = &hose->regions[i];