spl: use different BOARD_INIT MACRO for spl and tpl

[u-boot] / drivers / pci / pci-uclass.c

diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 40f59c0c4c439a3a97a982590b64fcfc9c57e52d..5a24eb6428f76b26b938ea63910744f74d64d20f 100644 (file)
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -8,12 +8,11 @@
 #include <common.h>
 #include <dm.h>
 #include <errno.h>
-#include <fdtdec.h>
 #include <inttypes.h>
 #include <pci.h>
 #include <asm/io.h>
-#include <dm/lists.h>
 #include <dm/device-internal.h>
+#include <dm/lists.h>
 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
 #include <asm/fsp/fsp_support.h>
 #endif
@@ -519,6 +518,64 @@ int pci_auto_config_devices(struct udevice *bus)
        return sub_bus;
 }
 
+int pci_generic_mmap_write_config(
+       struct udevice *bus,
+       int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
+       pci_dev_t bdf,
+       uint offset,
+       ulong value,
+       enum pci_size_t size)
+{
+       void *address;
+
+       if (addr_f(bus, bdf, offset, &address) < 0)
+               return 0;
+
+       switch (size) {
+       case PCI_SIZE_8:
+               writeb(value, address);
+               return 0;
+       case PCI_SIZE_16:
+               writew(value, address);
+               return 0;
+       case PCI_SIZE_32:
+               writel(value, address);
+               return 0;
+       default:
+               return -EINVAL;
+       }
+}
+
+int pci_generic_mmap_read_config(
+       struct udevice *bus,
+       int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
+       pci_dev_t bdf,
+       uint offset,
+       ulong *valuep,
+       enum pci_size_t size)
+{
+       void *address;
+
+       if (addr_f(bus, bdf, offset, &address) < 0) {
+               *valuep = pci_get_ff(size);
+               return 0;
+       }
+
+       switch (size) {
+       case PCI_SIZE_8:
+               *valuep = readb(address);
+               return 0;
+       case PCI_SIZE_16:
+               *valuep = readw(address);
+               return 0;
+       case PCI_SIZE_32:
+               *valuep = readl(address);
+               return 0;
+       default:
+               return -EINVAL;
+       }
+}
+
 int dm_pci_hose_probe_bus(struct udevice *bus)
 {
        int sub_bus;
@@ -660,6 +717,7 @@ static int pci_find_and_bind_driver(struct udevice *parent,
        ret = device_bind_driver(parent, drv, str, devp);
        if (ret) {
                debug("%s: Failed to bind generic driver: %d\n", __func__, ret);
+               free(str);
                return ret;
        }
        debug("%s: No match found: bound generic driver instead\n", __func__);
@@ -753,8 +811,8 @@ error:
        return ret;
 }
 
-static int decode_regions(struct pci_controller *hose, const void *blob,
-                         int parent_node, int node)
+static int decode_regions(struct pci_controller *hose, ofnode parent_node,
+                         ofnode node)
 {
        int pci_addr_cells, addr_cells, size_cells;
        phys_addr_t base = 0, size;
@@ -763,12 +821,12 @@ static int decode_regions(struct pci_controller *hose, const void *blob,
        int len;
        int i;
 
-       prop = fdt_getprop(blob, node, "ranges", &len);
+       prop = ofnode_get_property(node, "ranges", &len);
        if (!prop)
                return -EINVAL;
-       pci_addr_cells = fdt_address_cells(blob, node);
-       addr_cells = fdt_address_cells(blob, parent_node);
-       size_cells = fdt_size_cells(blob, node);
+       pci_addr_cells = ofnode_read_simple_addr_cells(node);
+       addr_cells = ofnode_read_simple_addr_cells(parent_node);
+       size_cells = ofnode_read_simple_size_cells(node);
 
        /* PCI addresses are always 3-cells */
        len /= sizeof(u32);
@@ -840,9 +898,8 @@ static int pci_uclass_pre_probe(struct udevice *bus)
        /* For bridges, use the top-level PCI controller */
        if (!device_is_on_pci_bus(bus)) {
                hose->ctlr = bus;
-               ret = decode_regions(hose, gd->fdt_blob,
-                                    dev_of_offset(bus->parent),
-                                    dev_of_offset(bus));
+               ret = decode_regions(hose, dev_ofnode(bus->parent),
+                                    dev_ofnode(bus));
                if (ret) {
                        debug("%s: Cannot decode regions\n", __func__);
                        return ret;
@@ -905,7 +962,7 @@ static int pci_uclass_child_post_bind(struct udevice *dev)
        struct fdt_pci_addr addr;
        int ret;
 
-       if (dev_of_offset(dev) == -1)
+       if (!dev_of_valid(dev))
                return 0;
 
        /*
@@ -913,8 +970,8 @@ static int pci_uclass_child_post_bind(struct udevice *dev)
         * just check the address.
         */
        pplat = dev_get_parent_platdata(dev);
-       ret = fdtdec_get_pci_addr(gd->fdt_blob, dev_of_offset(dev),
-                                 FDT_PCI_SPACE_CONFIG, "reg", &addr);
+       ret = ofnode_read_pci_addr(dev_ofnode(dev), FDT_PCI_SPACE_CONFIG, "reg",
+                                  &addr);
 
        if (ret) {
                if (ret != -ENOENT)