Merge git://git.denx.de/u-boot-usb

[u-boot] / drivers / pci / pci_auto.c

diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c
index 44470fa812b0ed42ca475bb27262d1b7be0fb733..e034ed1715cfcda988312bbb2dcce6cbea3177e2 100644 (file)
--- a/drivers/pci/pci_auto.c
+++ b/drivers/pci/pci_auto.c
@@ -11,18 +11,15 @@
  */
 
 #include <common.h>
-
+#include <errno.h>
 #include <pci.h>
 
-#undef DEBUG
 #ifdef DEBUG
 #define DEBUGF(x...) printf(x)
 #else
 #define DEBUGF(x...)
 #endif /* DEBUG */
 
-#define        PCIAUTO_IDE_MODE_MASK           0x05
-
 /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
 #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
@@ -90,6 +87,8 @@ void pciauto_setup_device(struct pci_controller *hose,
        pci_size_t bar_size;
        u16 cmdstat = 0;
        int bar, bar_nr = 0;
+       u8 header_type;
+       int rom_addr;
 #ifndef CONFIG_PCI_ENUM_ONLY
        pci_addr_t bar_value;
        struct pci_region *bar_res;
@@ -185,6 +184,26 @@ void pciauto_setup_device(struct pci_controller *hose,
                bar_nr++;
        }
 
+       /* Configure the expansion ROM address */
+       pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
+       if (header_type != PCI_HEADER_TYPE_CARDBUS) {
+               rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
+                          PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
+               pci_hose_write_config_dword(hose, dev, rom_addr, 0xfffffffe);
+               pci_hose_read_config_dword(hose, dev, rom_addr, &bar_response);
+               if (bar_response) {
+                       bar_size = -(bar_response & ~1);
+                       DEBUGF("PCI Autoconfig: ROM, size=%#x, ", bar_size);
+                       if (pciauto_region_allocate(mem, bar_size,
+                                                   &bar_value) == 0) {
+                               pci_hose_write_config_dword(hose, dev, rom_addr,
+                                                           bar_value);
+                       }
+                       cmdstat |= PCI_COMMAND_MEMORY;
+                       DEBUGF("\n");
+               }
+       }
+
        pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
        pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
                CONFIG_SYS_PCI_CACHE_LINE_SIZE);
@@ -197,9 +216,12 @@ void pciauto_prescan_setup_bridge(struct pci_controller *hose,
        struct pci_region *pci_mem = hose->pci_mem;
        struct pci_region *pci_prefetch = hose->pci_prefetch;
        struct pci_region *pci_io = hose->pci_io;
-       u16 cmdstat;
+       u16 cmdstat, prefechable_64;
 
        pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
+       pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
+                               &prefechable_64);
+       prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
 
        /* Configure bus number registers */
        pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
@@ -226,12 +248,26 @@ void pciauto_prescan_setup_bridge(struct pci_controller *hose,
                /* Set up memory and I/O filter limits, assume 32-bit I/O space */
                pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
                                        (pci_prefetch->bus_lower & 0xfff00000) >> 16);
+               if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
+#ifdef CONFIG_SYS_PCI_64BIT
+                       pci_hose_write_config_dword(hose, dev,
+                                       PCI_PREF_BASE_UPPER32,
+                                       pci_prefetch->bus_lower >> 32);
+#else
+                       pci_hose_write_config_dword(hose, dev,
+                                       PCI_PREF_BASE_UPPER32,
+                                       0x0);
+#endif
 
                cmdstat |= PCI_COMMAND_MEMORY;
        } else {
                /* We don't support prefetchable memory for now, so disable */
                pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
                pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
+               if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
+                       pci_hose_write_config_word(hose, dev, PCI_PREF_BASE_UPPER32, 0x0);
+                       pci_hose_write_config_word(hose, dev, PCI_PREF_LIMIT_UPPER32, 0x0);
+               }
        }
 
        if (pci_io) {
@@ -271,11 +307,28 @@ void pciauto_postscan_setup_bridge(struct pci_controller *hose,
        }
 
        if (pci_prefetch) {
+               u16 prefechable_64;
+
+               pci_hose_read_config_word(hose, dev,
+                                       PCI_PREF_MEMORY_LIMIT,
+                                       &prefechable_64);
+               prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
+
                /* Round memory allocator to 1MB boundary */
                pciauto_region_align(pci_prefetch, 0x100000);
 
                pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
                                (pci_prefetch->bus_lower - 1) >> 16);
+               if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
+#ifdef CONFIG_SYS_PCI_64BIT
+                       pci_hose_write_config_dword(hose, dev,
+                                       PCI_PREF_LIMIT_UPPER32,
+                                       (pci_prefetch->bus_lower - 1) >> 32);
+#else
+                       pci_hose_write_config_dword(hose, dev,
+                                       PCI_PREF_LIMIT_UPPER32,
+                                       0x0);
+#endif
        }
 
        if (pci_io) {
@@ -365,20 +418,26 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
 {
        unsigned int sub_bus = PCI_BUS(dev);
        unsigned short class;
-       unsigned char prg_iface;
        int n;
 
        pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
 
        switch (class) {
        case PCI_CLASS_BRIDGE_PCI:
-               hose->current_busno++;
+               DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n",
+                      PCI_DEV(dev));
+
                pciauto_setup_device(hose, dev, 2, hose->pci_mem,
                        hose->pci_prefetch, hose->pci_io);
 
-               DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_DEV(dev));
-
+#ifdef CONFIG_DM_PCI
+               n = dm_pci_hose_probe_bus(hose, dev);
+               if (n < 0)
+                       return n;
+               sub_bus = (unsigned int)n;
+#else
                /* Passing in current_busno allows for sibling P2P bridges */
+               hose->current_busno++;
                pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
                /*
                 * need to figure out if this is a subordinate bridge on the bus
@@ -391,17 +450,7 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
                pciauto_postscan_setup_bridge(hose, dev, sub_bus);
 
                sub_bus = hose->current_busno;
-               break;
-
-       case PCI_CLASS_STORAGE_IDE:
-               pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prg_iface);
-               if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
-                       DEBUGF("PCI Autoconfig: Skipping legacy mode IDE controller\n");
-                       return sub_bus;
-               }
-
-               pciauto_setup_device(hose, dev, 6, hose->pci_mem,
-                       hose->pci_prefetch, hose->pci_io);
+#endif
                break;
 
        case PCI_CLASS_BRIDGE_CARDBUS:
@@ -415,7 +464,9 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
                DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
                        PCI_DEV(dev));
 
+#ifndef CONFIG_DM_PCI
                hose->current_busno++;
+#endif
                break;
 
 #if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)