/*
* MVEBU PCIe controller needs MEMORY and I/O BARs to be mapped
- * into SoCs address space. Each controller will map 32M of MEM
+ * into SoCs address space. Each controller will map 128M of MEM
* and 64K of I/O space when registered.
*/
static void __iomem *mvebu_pcie_membase = (void __iomem *)MBUS_PCI_MEM_BASE;
-#define PCIE_MEM_SIZE (32 << 20)
+#define PCIE_MEM_SIZE (128 << 20)
#if defined(CONFIG_ARMADA_38X)
#define PCIE_BASE(if) \