spi: mxc: Fix compilation problem of DM_SPI class driver

[u-boot] / drivers / pci / pci_sh7751.c

diff --git a/drivers/pci/pci_sh7751.c b/drivers/pci/pci_sh7751.c
index df6d76f7f17cf1a895f8d0ef29c6be81ab3d16a5..2f918f161a0340cd13d4ea3865de2245c51f3576 100644 (file)
--- a/drivers/pci/pci_sh7751.c
+++ b/drivers/pci/pci_sh7751.c
@@ -1,25 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * SH7751 PCI Controller (PCIC) for U-Boot.
  * (C) Dustin McIntire (dustin@sensoria.com)
  * (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
  */
 
 #include <common.h>
@@ -82,9 +65,6 @@
 #define SH7751_PCI_IO_BASE             0xFE240000
 #define SH7751_PCI_IO_SIZE             0x00040000
 
-#define SH7751_CS3_BASE_ADDR    0x0C000000
-#define SH7751_P2CS3_BASE_ADDR  0xAC000000
-
 #define SH7751_PCIPAR   (vu_long *)0xFE2001C0
 #define SH7751_PCIPDR   (vu_long *)0xFE200220
 
@@ -169,18 +149,19 @@ int pci_sh7751_init(struct pci_controller *hose)
 
        /* Set up target memory mappings (for external DMA access) */
        /* Map both P0 and P2 range to Area 3 RAM for ease of use */
-       p4_out((64 - 1) << 20, SH7751_PCILSR0);
-       p4_out(SH7751_CS3_BASE_ADDR, SH7751_PCILAR0);
+       p4_out(CONFIG_SYS_SDRAM_SIZE - 0x100000, SH7751_PCILSR0);
+       p4_out(CONFIG_SYS_SDRAM_BASE & 0x1FF00000, SH7751_PCILAR0);
+       p4_out(CONFIG_SYS_SDRAM_BASE & 0xFFF00000, SH7751_PCICONF5);
+
        p4_out(0, SH7751_PCILSR1);
        p4_out(0, SH7751_PCILAR1);
-       p4_out(SH7751_CS3_BASE_ADDR, SH7751_PCICONF5);
        p4_out(0xd0000000, SH7751_PCICONF6);
 
        /* Map memory window to same address on PCI bus */
        p4_out(SH7751_PCI_MEM_BASE, SH7751_PCIMBR);
 
        /* Map IO window to same address on PCI bus */
-       p4_out(0x2000 & 0xfffc0000, SH7751_PCIIOBR);
+       p4_out(SH7751_PCI_IO_BASE, SH7751_PCIIOBR);
 
        /* set BREQEN */
        p4_out(inl(SH7751_BCR1) | 0x00080000, SH7751_BCR1);