#include <asm/arch/clock.h>
#include <asm/arch/iomux.h>
#include <asm/arch/crm_regs.h>
+#include <asm/gpio.h>
#include <asm/io.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#include <errno.h>
+#include <asm/arch/sys_proto.h>
#define PCI_ACCESS_READ 0
#define PCI_ACCESS_WRITE 1
+#ifdef CONFIG_MX6SX
+#define MX6_DBI_ADDR 0x08ffc000
+#define MX6_IO_ADDR 0x08000000
+#define MX6_MEM_ADDR 0x08100000
+#define MX6_ROOT_ADDR 0x08f00000
+#else
#define MX6_DBI_ADDR 0x01ffc000
-#define MX6_DBI_SIZE 0x4000
#define MX6_IO_ADDR 0x01000000
-#define MX6_IO_SIZE 0x100000
#define MX6_MEM_ADDR 0x01100000
-#define MX6_MEM_SIZE 0xe00000
#define MX6_ROOT_ADDR 0x01f00000
+#endif
+#define MX6_DBI_SIZE 0x4000
+#define MX6_IO_SIZE 0x100000
+#define MX6_MEM_SIZE 0xe00000
#define MX6_ROOT_SIZE 0xfc000
/* PCIe Port Logic registers (memory-mapped) */
#define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
#define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
+#define PCIE_PHY_PUP_REQ (1 << 7)
+
/* iATU registers */
#define PCIE_ATU_VIEWPORT 0x900
#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
ret = imx_pcie_addr_valid(d);
if (ret) {
*val = 0xffffffff;
- return ret;
+ return 0;
}
va_address = get_bus_address(d, where);
{
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ if (is_mx6dqp())
+ setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
+
+#if defined(CONFIG_MX6SX)
+ struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;
+
+ /* SSP_EN is not used on MX6SX anymore */
+ setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
+ /* Force PCIe PHY reset */
+ setbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
+ /* Power up PCIe PHY */
+ setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ);
+#else
setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
+#endif
return 0;
}
IOMUXC_GPR12_LOS_LEVEL_MASK,
IOMUXC_GPR12_LOS_LEVEL_9);
+#ifdef CONFIG_MX6SX
+ clrsetbits_le32(&iomuxc_regs->gpr[12],
+ IOMUXC_GPR12_RX_EQ_MASK,
+ IOMUXC_GPR12_RX_EQ_2);
+#endif
+
writel((0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET) |
(0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET) |
(20 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET) |
return 0;
}
+__weak int imx6_pcie_toggle_power(void)
+{
+#ifdef CONFIG_PCIE_IMX_POWER_GPIO
+ gpio_direction_output(CONFIG_PCIE_IMX_POWER_GPIO, 0);
+ mdelay(20);
+ gpio_set_value(CONFIG_PCIE_IMX_POWER_GPIO, 1);
+ mdelay(20);
+#endif
+ return 0;
+}
+
+__weak int imx6_pcie_toggle_reset(void)
+{
+ /*
+ * See 'PCI EXPRESS BASE SPECIFICATION, REV 3.0, SECTION 6.6.1'
+ * for detailed understanding of the PCIe CR reset logic.
+ *
+ * The PCIe #PERST reset line _MUST_ be connected, otherwise your
+ * design does not conform to the specification. You must wait at
+ * least 20 ms after de-asserting the #PERST so the EP device can
+ * do self-initialisation.
+ *
+ * In case your #PERST pin is connected to a plain GPIO pin of the
+ * CPU, you can define CONFIG_PCIE_IMX_PERST_GPIO in your board's
+ * configuration file and the condition below will handle the rest
+ * of the reset toggling.
+ *
+ * In case your #PERST toggling logic is more complex, for example
+ * connected via CPLD or somesuch, you can override this function
+ * in your board file and implement reset logic as needed. You must
+ * not forget to wait at least 20 ms after de-asserting #PERST in
+ * this case either though.
+ *
+ * In case your #PERST line of the PCIe EP device is not connected
+ * at all, your design is broken and you should fix your design,
+ * otherwise you will observe problems like for example the link
+ * not coming up after rebooting the system back from running Linux
+ * that uses the PCIe as well OR the PCIe link might not come up in
+ * Linux at all in the first place since it's in some non-reset
+ * state due to being previously used in U-Boot.
+ */
+#ifdef CONFIG_PCIE_IMX_PERST_GPIO
+ gpio_direction_output(CONFIG_PCIE_IMX_PERST_GPIO, 0);
+ mdelay(20);
+ gpio_set_value(CONFIG_PCIE_IMX_PERST_GPIO, 1);
+ mdelay(20);
+#else
+ puts("WARNING: Make sure the PCIe #PERST line is connected!\n");
+#endif
+ return 0;
+}
+
static int imx6_pcie_deassert_core_reset(void)
{
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
- /* FIXME: Power-up GPIO goes here. */
-
- /* Enable PCIe */
- clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
- setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
+ imx6_pcie_toggle_power();
enable_pcie_clock();
+ if (is_mx6dqp())
+ clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
+
/*
* Wait for the clock to settle a bit, when the clock are sourced
- * from the CPU, we need about 30mS to settle.
+ * from the CPU, we need about 30 ms to settle.
*/
- mdelay(30);
+ mdelay(50);
+
+#if defined(CONFIG_MX6SX)
+ /* SSP_EN is not used on MX6SX anymore */
+ clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
+ /* Clear PCIe PHY reset bit */
+ clrbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
+#else
+ /* Enable PCIe */
+ clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
+ setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
+#endif
- /* FIXME: GPIO reset goes here */
- mdelay(100);
+ imx6_pcie_toggle_reset();
return 0;
}
udelay(10);
count++;
if (count >= 2000) {
- debug("phy link never came up\n");
+#ifdef CONFIG_PCI_SCAN_SHOW
+ puts("PCI: pcie phy link never came up\n");
+#endif
debug("DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R0),
readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R1));