dm: pci: Tidy up auto-config error handling

[u-boot] / drivers / pci / pcie_imx.c

diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c
index fd7e4d499f06b01fa8bd5a491b7eaaccff0943d3..f1e189edd5c85ee3e2c59349af4a0792b374a83e 100644 (file)
--- a/drivers/pci/pcie_imx.c
+++ b/drivers/pci/pcie_imx.c
@@ -19,6 +19,7 @@
 #include <asm/io.h>
 #include <linux/sizes.h>
 #include <errno.h>
+#include <asm/arch/sys_proto.h>
 
 #define PCI_ACCESS_READ  0
 #define PCI_ACCESS_WRITE 1
@@ -430,6 +431,10 @@ static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
 static int imx6_pcie_assert_core_reset(void)
 {
        struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+       if (is_mx6dqp())
+               setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
+
 #if defined(CONFIG_MX6SX)
        struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;
 
@@ -495,7 +500,7 @@ __weak int imx6_pcie_toggle_reset(void)
         *
         * The PCIe #PERST reset line _MUST_ be connected, otherwise your
         * design does not conform to the specification. You must wait at
-        * least 20 mS after de-asserting the #PERST so the EP device can
+        * least 20 ms after de-asserting the #PERST so the EP device can
         * do self-initialisation.
         *
         * In case your #PERST pin is connected to a plain GPIO pin of the
@@ -506,7 +511,7 @@ __weak int imx6_pcie_toggle_reset(void)
         * In case your #PERST toggling logic is more complex, for example
         * connected via CPLD or somesuch, you can override this function
         * in your board file and implement reset logic as needed. You must
-        * not forget to wait at least 20 mS after de-asserting #PERST in
+        * not forget to wait at least 20 ms after de-asserting #PERST in
         * this case either though.
         *
         * In case your #PERST line of the PCIe EP device is not connected
@@ -536,9 +541,12 @@ static int imx6_pcie_deassert_core_reset(void)
 
        enable_pcie_clock();
 
+       if (is_mx6dqp())
+               clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
+
        /*
         * Wait for the clock to settle a bit, when the clock are sourced
-        * from the CPU, we need about 30mS to settle.
+        * from the CPU, we need about 30 ms to settle.
         */
        mdelay(50);
 
@@ -588,7 +596,9 @@ static int imx_pcie_link_up(void)
                udelay(10);
                count++;
                if (count >= 2000) {
-                       debug("phy link never came up\n");
+#ifdef CONFIG_PCI_SCAN_SHOW
+                       puts("PCI:   pcie phy link never came up\n");
+#endif
                        debug("DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
                              readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R0),
                              readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R1));