sbc8641d: increase malloc pool size to a sane default

[u-boot] / drivers / pci / pcie_imx.c

diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c
index 1568f20c1a060bfd28e633088acc1644fa51b571..f1e189edd5c85ee3e2c59349af4a0792b374a83e 100644 (file)
--- a/drivers/pci/pcie_imx.c
+++ b/drivers/pci/pcie_imx.c
@@ -19,6 +19,7 @@
 #include <asm/io.h>
 #include <linux/sizes.h>
 #include <errno.h>
+#include <asm/arch/sys_proto.h>
 
 #define PCI_ACCESS_READ  0
 #define PCI_ACCESS_WRITE 1
@@ -430,6 +431,10 @@ static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
 static int imx6_pcie_assert_core_reset(void)
 {
        struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+       if (is_mx6dqp())
+               setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
+
 #if defined(CONFIG_MX6SX)
        struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;
 
@@ -536,6 +541,9 @@ static int imx6_pcie_deassert_core_reset(void)
 
        enable_pcie_clock();
 
+       if (is_mx6dqp())
+               clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
+
        /*
         * Wait for the clock to settle a bit, when the clock are sourced
         * from the CPU, we need about 30 ms to settle.