net: gem: Check return value from memalign/malloc

[u-boot] / drivers / pci / pcie_imx.c

diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c
index eab0a2b602f884c9934c01d6fb22b51393fa2153..fcc4ab713923aec381fc97cf053e54f17101205d 100644 (file)
--- a/drivers/pci/pcie_imx.c
+++ b/drivers/pci/pcie_imx.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Freescale i.MX6 PCI Express Root-Complex driver
  *
@@ -6,8 +7,6 @@
  * Based on upstream Linux kernel driver:
  * pci-imx6.c:         Sean Cross <xobs@kosagi.com>
  * pcie-designware.c:  Jingoo Han <jg1.han@samsung.com>
- *
- * SPDX-License-Identifier:    GPL-2.0
  */
 
 #include <common.h>
@@ -431,7 +430,7 @@ static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
 /*
  * Initial bus setup
  */
-static int imx6_pcie_assert_core_reset(void)
+static int imx6_pcie_assert_core_reset(bool prepare_for_boot)
 {
        struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 
@@ -459,7 +458,7 @@ static int imx6_pcie_assert_core_reset(void)
         * If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have a strong
         * indication that the bootloader activated the link.
         */
-       if (is_mx6dq()) {
+       if (is_mx6dq() && prepare_for_boot) {
                u32 val, gpr1, gpr12;
 
                gpr1 = readl(&iomuxc_regs->gpr[1]);
@@ -517,10 +516,12 @@ static int imx6_pcie_init_phy(void)
 __weak int imx6_pcie_toggle_power(void)
 {
 #ifdef CONFIG_PCIE_IMX_POWER_GPIO
+       gpio_request(CONFIG_PCIE_IMX_POWER_GPIO, "pcie_power");
        gpio_direction_output(CONFIG_PCIE_IMX_POWER_GPIO, 0);
        mdelay(20);
        gpio_set_value(CONFIG_PCIE_IMX_POWER_GPIO, 1);
        mdelay(20);
+       gpio_free(CONFIG_PCIE_IMX_POWER_GPIO);
 #endif
        return 0;
 }
@@ -556,10 +557,12 @@ __weak int imx6_pcie_toggle_reset(void)
         * state due to being previously used in U-Boot.
         */
 #ifdef CONFIG_PCIE_IMX_PERST_GPIO
+       gpio_request(CONFIG_PCIE_IMX_PERST_GPIO, "pcie_reset");
        gpio_direction_output(CONFIG_PCIE_IMX_PERST_GPIO, 0);
        mdelay(20);
        gpio_set_value(CONFIG_PCIE_IMX_PERST_GPIO, 1);
        mdelay(20);
+       gpio_free(CONFIG_PCIE_IMX_PERST_GPIO);
 #else
        puts("WARNING: Make sure the PCIe #PERST line is connected!\n");
 #endif
@@ -605,12 +608,23 @@ static int imx_pcie_link_up(void)
        uint32_t tmp;
        int count = 0;
 
-       imx6_pcie_assert_core_reset();
+       imx6_pcie_assert_core_reset(false);
        imx6_pcie_init_phy();
        imx6_pcie_deassert_core_reset();
 
        imx_pcie_regions_setup();
 
+       /*
+        * By default, the subordinate is set equally to the secondary
+        * bus (0x01) when the RC boots.
+        * This means that theoretically, only bus 1 is reachable from the RC.
+        * Force the PCIe RC subordinate to 0xff, otherwise no downstream
+        * devices will be detected if the enumeration is applied strictly.
+        */
+       tmp = readl(MX6_DBI_ADDR + 0x18);
+       tmp |= (0xff << 16);
+       writel(tmp, MX6_DBI_ADDR + 0x18);
+
        /*
         * FIXME: Force the PCIe RC to Gen1 operation
         * The RC must be forced into Gen1 mode before bringing the link
@@ -687,7 +701,7 @@ void imx_pcie_init(void)
 
 void imx_pcie_remove(void)
 {
-       imx6_pcie_assert_core_reset();
+       imx6_pcie_assert_core_reset(true);
 }
 
 /* Probe function. */