x86: pci: Allow conditionally run VGA rom in S3

[u-boot] / drivers / pci / pcie_layerscape.c

diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 90b9fe2a17a82b34136754adaa9ea5b2cf590da5..1c5a33ac2835275f84a73fb299f0c4f24caf5fe7 100644 (file)
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -167,6 +167,27 @@ static void ls_pcie_setup_atu(struct ls_pcie *pcie)
        pci_get_regions(pcie->bus, &io, &mem, &pref);
        idx = PCIE_ATU_REGION_INDEX1 + 1;
 
+       /* Fix the pcie memory map for LS2088A series SoCs */
+       svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
+       if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
+           svr == SVR_LS2048A || svr == SVR_LS2044A) {
+               if (io)
+                       io->phys_start = (io->phys_start &
+                                        (PCIE_PHYS_SIZE - 1)) +
+                                        LS2088A_PCIE1_PHYS_ADDR +
+                                        LS2088A_PCIE_PHYS_SIZE * pcie->idx;
+               if (mem)
+                       mem->phys_start = (mem->phys_start &
+                                        (PCIE_PHYS_SIZE - 1)) +
+                                        LS2088A_PCIE1_PHYS_ADDR +
+                                        LS2088A_PCIE_PHYS_SIZE * pcie->idx;
+               if (pref)
+                       pref->phys_start = (pref->phys_start &
+                                        (PCIE_PHYS_SIZE - 1)) +
+                                        LS2088A_PCIE1_PHYS_ADDR +
+                                        LS2088A_PCIE_PHYS_SIZE * pcie->idx;
+       }
+
        if (io)
                /* ATU : OUTBOUND : IO */
                ls_pcie_atu_outbound_set(pcie, idx++,
@@ -409,6 +430,11 @@ static void ls_pcie_ep_setup_bars(void *bar_base)
        ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE);
 }
 
+static void ls_pcie_ep_enable_cfg(struct ls_pcie *pcie)
+{
+       ctrl_writel(pcie, PCIE_CONFIG_READY, PCIE_PF_CONFIG);
+}
+
 static void ls_pcie_setup_ep(struct ls_pcie *pcie)
 {
        u32 sriov;
@@ -432,16 +458,19 @@ static void ls_pcie_setup_ep(struct ls_pcie *pcie)
                ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE);
                ls_pcie_ep_setup_atu(pcie);
        }
+
+       ls_pcie_ep_enable_cfg(pcie);
 }
 
 static int ls_pcie_probe(struct udevice *dev)
 {
        struct ls_pcie *pcie = dev_get_priv(dev);
        const void *fdt = gd->fdt_blob;
-       int node = dev->of_offset;
+       int node = dev_of_offset(dev);
        u8 header_type;
        u16 link_sta;
        bool ep_mode;
+       uint svr;
        int ret;
 
        pcie->bus = dev;
@@ -495,6 +524,19 @@ static int ls_pcie_probe(struct udevice *dev)
                return ret;
        }
 
+       /*
+        * Fix the pcie memory map address and PF control registers address
+        * for LS2088A series SoCs
+        */
+       svr = get_svr();
+       svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
+       if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
+           svr == SVR_LS2048A || svr == SVR_LS2044A) {
+               pcie->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR +
+                                       LS2088A_PCIE_PHYS_SIZE * pcie->idx;
+               pcie->ctrl = pcie->lut + 0x40000;
+       }
+
        pcie->cfg0 = map_physmem(pcie->cfg_res.start,
                                 fdt_resource_size(&pcie->cfg_res),
                                 MAP_NOCACHE);