Merge git://git.denx.de/u-boot-sunxi

[u-boot] / drivers / pci / pcie_layerscape.c

diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 1c5a33ac2835275f84a73fb299f0c4f24caf5fe7..610f85c4e8ea464edc531ba4af4fa252d5b24044 100644 (file)
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -1,4 +1,5 @@
 /*
+ * Copyright 2017 NXP
  * Copyright 2014-2015 Freescale Semiconductor, Inc.
  * Layerscape PCIe driver
  *
@@ -12,6 +13,10 @@
 #include <errno.h>
 #include <malloc.h>
 #include <dm.h>
+#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
+       defined(CONFIG_ARM)
+#include <asm/arch/clock.h>
+#endif
 #include "pcie_layerscape.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -170,7 +175,8 @@ static void ls_pcie_setup_atu(struct ls_pcie *pcie)
        /* Fix the pcie memory map for LS2088A series SoCs */
        svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
        if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
-           svr == SVR_LS2048A || svr == SVR_LS2044A) {
+           svr == SVR_LS2048A || svr == SVR_LS2044A ||
+           svr == SVR_LS2081A || svr == SVR_LS2041A) {
                if (io)
                        io->phys_start = (io->phys_start &
                                         (PCIE_PHYS_SIZE - 1)) +
@@ -472,6 +478,7 @@ static int ls_pcie_probe(struct udevice *dev)
        bool ep_mode;
        uint svr;
        int ret;
+       fdt_size_t cfg_size;
 
        pcie->bus = dev;
 
@@ -531,9 +538,12 @@ static int ls_pcie_probe(struct udevice *dev)
        svr = get_svr();
        svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
        if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
-           svr == SVR_LS2048A || svr == SVR_LS2044A) {
+           svr == SVR_LS2048A || svr == SVR_LS2044A ||
+           svr == SVR_LS2081A || svr == SVR_LS2041A) {
+               cfg_size = fdt_resource_size(&pcie->cfg_res);
                pcie->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR +
                                        LS2088A_PCIE_PHYS_SIZE * pcie->idx;
+               pcie->cfg_res.end = pcie->cfg_res.start + cfg_size;
                pcie->ctrl = pcie->lut + 0x40000;
        }