Merge branch 'master' of git://git.denx.de/u-boot-spi

[u-boot] / drivers / pci / pcie_layerscape.h

diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h
index 5e893d4a8bead13004693951101877a5f7c1b221..8770b44a1f0096c2247f884d6bd1eae6b64f2fe6 100644 (file)
--- a/drivers/pci/pcie_layerscape.h
+++ b/drivers/pci/pcie_layerscape.h
@@ -1,13 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
+ * Copyright 2017 NXP
  * Copyright 2014-2015 Freescale Semiconductor, Inc.
  * Layerscape PCIe driver
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef _PCIE_LAYERSCAPE_H_
 #define _PCIE_LAYERSCAPE_H_
 #include <pci.h>
+#include <dm.h>
 
 #ifndef CONFIG_SYS_PCI_MEMORY_BUS
 #define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE
@@ -25,6 +26,10 @@
 #define CONFIG_SYS_PCI_EP_MEMORY_BASE CONFIG_SYS_LOAD_ADDR
 #endif
 
+#define PCIE_PHYS_SIZE                 0x200000000
+#define LS2088A_PCIE_PHYS_SIZE         0x800000000
+#define LS2088A_PCIE1_PHYS_ADDR                0x2000000000
+
 /* iATU registers */
 #define PCIE_ATU_VIEWPORT              0x900
 #define PCIE_ATU_REGION_INBOUND                (0x1 << 31)
@@ -86,57 +91,6 @@
 #define PCIE_BAR2_SIZE         (4 * 1024) /* 4K */
 #define PCIE_BAR4_SIZE         (1 * 1024 * 1024) /* 1M */
 
-#ifndef CONFIG_DM_PCI
-struct ls_pcie {
-       int idx;
-       void __iomem *dbi;
-       void __iomem *va_cfg0;
-       void __iomem *va_cfg1;
-       int next_lut_index;
-       struct pci_controller hose;
-};
-
-struct ls_pcie_info {
-       unsigned long regs;
-       int pci_num;
-       u64 phys_base;
-       u64 cfg0_phys;
-       u64 cfg0_size;
-       u64 cfg1_phys;
-       u64 cfg1_size;
-       u64 mem_bus;
-       u64 mem_phys;
-       u64 mem_size;
-       u64 io_bus;
-       u64 io_phys;
-       u64 io_size;
-};
-
-#define SET_LS_PCIE_INFO(x, num)                       \
-{                                                      \
-       x.regs = CONFIG_SYS_PCIE##num##_ADDR;           \
-       x.phys_base = CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
-       x.cfg0_phys = CONFIG_SYS_PCIE_CFG0_PHYS_OFF +   \
-                     CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
-       x.cfg0_size = CONFIG_SYS_PCIE_CFG0_SIZE;        \
-       x.cfg1_phys = CONFIG_SYS_PCIE_CFG1_PHYS_OFF +   \
-                     CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
-       x.cfg1_size = CONFIG_SYS_PCIE_CFG1_SIZE;        \
-       x.mem_bus = CONFIG_SYS_PCIE_MEM_BUS;            \
-       x.mem_phys = CONFIG_SYS_PCIE_MEM_PHYS_OFF +     \
-                    CONFIG_SYS_PCIE##num##_PHYS_ADDR;  \
-       x.mem_size = CONFIG_SYS_PCIE_MEM_SIZE;          \
-       x.io_bus = CONFIG_SYS_PCIE_IO_BUS;              \
-       x.io_phys = CONFIG_SYS_PCIE_IO_PHYS_OFF +       \
-                   CONFIG_SYS_PCIE##num##_PHYS_ADDR;   \
-       x.io_size = CONFIG_SYS_PCIE_IO_SIZE;            \
-       x.pci_num = num;                                \
-}
-
-#else /* CONFIG_DM_PCI */
-
-#include <dm.h>
-
 /* LUT registers */
 #define PCIE_LUT_UDR(n)                (0x800 + (n) * 8)
 #define PCIE_LUT_LDR(n)                (0x804 + (n) * 8)
@@ -144,8 +98,10 @@ struct ls_pcie_info {
 #define PCIE_LUT_ENTRY_COUNT   32
 
 /* PF Controll registers */
+#define PCIE_PF_CONFIG         0x14
 #define PCIE_PF_VF_CTRL                0x7F8
 #define PCIE_PF_DBG            0x7FC
+#define PCIE_CONFIG_READY      (1 << 0)
 
 #define PCIE_SRDS_PRTCL(idx)   (PCIE1 + (idx))
 #define PCIE_SYS_BASE_ADDR     0x3400000
@@ -157,6 +113,12 @@ struct ls_pcie_info {
 #define SVR_LS102XA            0
 #define SVR_VAR_PER_SHIFT      8
 #define SVR_LS102XA_MASK       0x700
+#define SVR_LS2088A            0x870900
+#define SVR_LS2084A            0x870910
+#define SVR_LS2048A            0x870920
+#define SVR_LS2044A            0x870930
+#define SVR_LS2081A            0x870918
+#define SVR_LS2041A            0x870914
 
 /* LS1021a PCIE space */
 #define LS1021_PCIE_SPACE_OFFSET       0x4000000000ULL
@@ -182,10 +144,8 @@ struct ls_pcie {
        bool big_endian;
        bool enabled;
        int next_lut_index;
-       struct pci_controller hose;
 };
 
 extern struct list_head ls_pcie_list;
 
-#endif /* CONFIG_DM_PCI */
 #endif /* _PCIE_LAYERSCAPE_H_ */