]> git.sur5r.net Git - u-boot/blobdiff - drivers/pinctrl/renesas/sh_pfc.h
pinctrl: rmobile: Import R8A7791/R8A7793 M2 PFC tables
[u-boot] / drivers / pinctrl / renesas / sh_pfc.h
index 7aef2d360b26bcd13f7bbb0bf21833c5fa13ed16..96c8ea3b3ff517944ad66452e0d4afea86fc91c8 100644 (file)
@@ -243,9 +243,15 @@ void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width, u32 data)
 const struct sh_pfc_bias_info *
 sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info,
                        unsigned int num, unsigned int pin);
+int sh_pfc_config_mux_for_gpio(struct udevice *dev, unsigned pin_selector);
 
+extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
+extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
+extern const struct sh_pfc_soc_info r8a7793_pinmux_info;
 extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
 extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
+extern const struct sh_pfc_soc_info r8a77970_pinmux_info;
+extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
 /* -----------------------------------------------------------------------------
  * Helper macros to create pin and port lists
  */
@@ -337,6 +343,11 @@ extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
        PORT_GP_CFG_1(bank, 3,  fn, sfx, cfg)
 #define PORT_GP_4(bank, fn, sfx)       PORT_GP_CFG_4(bank, fn, sfx, 0)
 
+#define PORT_GP_CFG_6(bank, fn, sfx, cfg)                              \
+       PORT_GP_CFG_4(bank, fn, sfx, cfg),                              \
+       PORT_GP_CFG_1(bank, 4,  fn, sfx, cfg), PORT_GP_CFG_1(bank, 5,  fn, sfx, cfg)
+#define PORT_GP_6(bank, fn, sfx)       PORT_GP_CFG_6(bank, fn, sfx, 0)
+
 #define PORT_GP_CFG_8(bank, fn, sfx, cfg)                              \
        PORT_GP_CFG_4(bank, fn, sfx, cfg),                              \
        PORT_GP_CFG_1(bank, 4,  fn, sfx, cfg),                          \
@@ -398,6 +409,12 @@ extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
        PORT_GP_CFG_1(bank, 20, fn, sfx, cfg)
 #define PORT_GP_21(bank, fn, sfx)      PORT_GP_CFG_21(bank, fn, sfx, 0)
 
+#define PORT_GP_CFG_22(bank, fn, sfx, cfg)                             \
+       PORT_GP_CFG_18(bank, fn, sfx, cfg),                             \
+       PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), PORT_GP_CFG_1(bank, 19, fn, sfx, cfg),   \
+       PORT_GP_CFG_1(bank, 20, fn, sfx, cfg), PORT_GP_CFG_1(bank, 21, fn, sfx, cfg)
+#define PORT_GP_22(bank, fn, sfx)      PORT_GP_CFG_22(bank, fn, sfx, 0)
+
 #define PORT_GP_CFG_23(bank, fn, sfx, cfg)                             \
        PORT_GP_CFG_21(bank, fn, sfx, cfg),                             \
        PORT_GP_CFG_1(bank, 21, fn, sfx, cfg),                          \