dm: core: Add logging of some common errors

[u-boot] / drivers / pwm / rk_pwm.c

diff --git a/drivers/pwm/rk_pwm.c b/drivers/pwm/rk_pwm.c
index 2d289a4c07f12d583116397643467e3424735bbe..9994cbafbffd8614ba4d45d6df7a72cb246167b9 100644 (file)
--- a/drivers/pwm/rk_pwm.c
+++ b/drivers/pwm/rk_pwm.c
@@ -1,30 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (c) 2016 Google, Inc
  * Written by Simon Glass <sjg@chromium.org>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
+#include <clk.h>
 #include <div64.h>
 #include <dm.h>
 #include <pwm.h>
 #include <regmap.h>
 #include <syscon.h>
 #include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cru_rk3288.h>
-#include <asm/arch/grf_rk3288.h>
 #include <asm/arch/pwm.h>
 #include <power/regulator.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
 struct rk_pwm_priv {
        struct rk3288_pwm *regs;
-       struct rk3288_grf *grf;
+       ulong freq;
+       uint enable_conf;
 };
 
+static int rk_pwm_set_invert(struct udevice *dev, uint channel, bool polarity)
+{
+       struct rk_pwm_priv *priv = dev_get_priv(dev);
+
+       debug("%s: polarity=%u\n", __func__, polarity);
+       priv->enable_conf &= ~(PWM_DUTY_MASK | PWM_INACTIVE_MASK);
+       if (polarity)
+               priv->enable_conf |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSTIVE;
+       else
+               priv->enable_conf |= PWM_DUTY_POSTIVE | PWM_INACTIVE_NEGATIVE;
+
+       return 0;
+}
+
 static int rk_pwm_set_config(struct udevice *dev, uint channel, uint period_ns,
                             uint duty_ns)
 {
@@ -34,12 +44,12 @@ static int rk_pwm_set_config(struct udevice *dev, uint channel, uint period_ns,
 
        debug("%s: period_ns=%u, duty_ns=%u\n", __func__, period_ns, duty_ns);
        writel(PWM_SEL_SRC_CLK | PWM_OUTPUT_LEFT | PWM_LP_DISABLE |
-               PWM_CONTINUOUS | PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE |
+               PWM_CONTINUOUS | priv->enable_conf |
                RK_PWM_DISABLE,
                &regs->ctrl);
 
-       period = lldiv((uint64_t)(PD_BUS_PCLK_HZ / 1000) * period_ns, 1000000);
-       duty = lldiv((uint64_t)(PD_BUS_PCLK_HZ / 1000) * duty_ns, 1000000);
+       period = lldiv((uint64_t)(priv->freq / 1000) * period_ns, 1000000);
+       duty = lldiv((uint64_t)(priv->freq / 1000) * duty_ns, 1000000);
 
        writel(period, &regs->period_hpr);
        writel(duty, &regs->duty_lpr);
@@ -62,13 +72,8 @@ static int rk_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
 static int rk_pwm_ofdata_to_platdata(struct udevice *dev)
 {
        struct rk_pwm_priv *priv = dev_get_priv(dev);
-       struct regmap *map;
 
-       priv->regs = (struct rk3288_pwm *)dev_get_addr(dev);
-       map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_GRF);
-       if (IS_ERR(map))
-               return PTR_ERR(map);
-       priv->grf = regmap_get_range(map, 0);
+       priv->regs = (struct rk3288_pwm *)dev_read_addr(dev);
 
        return 0;
 }
@@ -76,13 +81,22 @@ static int rk_pwm_ofdata_to_platdata(struct udevice *dev)
 static int rk_pwm_probe(struct udevice *dev)
 {
        struct rk_pwm_priv *priv = dev_get_priv(dev);
+       struct clk clk;
+       int ret = 0;
 
-       rk_setreg(&priv->grf->soc_con2, 1 << 0);
+       ret = clk_get_by_index(dev, 0, &clk);
+       if (ret < 0) {
+               debug("%s get clock fail!\n", __func__);
+               return -EINVAL;
+       }
+       priv->freq = clk_get_rate(&clk);
+       priv->enable_conf = PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE;
 
        return 0;
 }
 
 static const struct pwm_ops rk_pwm_ops = {
+       .set_invert     = rk_pwm_set_invert,
        .set_config     = rk_pwm_set_config,
        .set_enable     = rk_pwm_set_enable,
 };