microblaze: Enable OF_CONTROL by default

[u-boot] / drivers / qe / qe.c

diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index bc946731a1eb20aa670722a9bdde67efb1d20eee..08620b23a7180fba914626b471a9de5ed099b90a 100644 (file)
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -13,6 +13,9 @@
 #include "asm/io.h"
 #include "linux/immap_qe.h"
 #include "qe.h"
+#ifdef CONFIG_LS102XA
+#include <asm/arch/immap_ls102xa.h>
+#endif
 
 #define MPC85xx_DEVDISR_QE_DISABLE     0x1
 
@@ -193,6 +196,18 @@ void u_qe_init(void)
 }
 #endif
 
+#ifdef CONFIG_U_QE
+void u_qe_resume(void)
+{
+       qe_map_t *qe_immrr;
+       uint qe_base = CONFIG_SYS_IMMR + QE_IMMR_OFFSET; /* QE immr base */
+       qe_immrr = (qe_map_t *)qe_base;
+
+       u_qe_firmware_resume((const void *)CONFIG_SYS_QE_FW_ADDR, qe_immrr);
+       out_be32(&qe_immrr->iram.iready, QE_IRAM_READY);
+}
+#endif
+
 void qe_reset(void)
 {
        qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID,
@@ -298,9 +313,10 @@ static void qe_upload_microcode(const void *base,
 
        if (ucode->major || ucode->minor || ucode->revision)
                printf("QE: uploading microcode '%s' version %u.%u.%u\n",
-                       ucode->id, ucode->major, ucode->minor, ucode->revision);
+                      (char *)ucode->id, (u16)ucode->major, (u16)ucode->minor,
+                      (u16)ucode->revision);
        else
-               printf("QE: uploading microcode '%s'\n", ucode->id);
+               printf("QE: uploading microcode '%s'\n", (char *)ucode->id);
 
        /* Use auto-increment */
        out_be32(&qe_immr->iram.iadd, be32_to_cpu(ucode->iram_offset) |
@@ -335,7 +351,11 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
        size_t length;
        const struct qe_header *hdr;
 #ifdef CONFIG_DEEP_SLEEP
+#ifdef CONFIG_LS102XA
+       struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+#else
        ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#endif
 #endif
        if (!firmware) {
                printf("Invalid address\n");
@@ -415,7 +435,7 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
         * saved microcode information and put in the new.
         */
        memset(&qe_firmware_info, 0, sizeof(qe_firmware_info));
-       strcpy(qe_firmware_info.id, (char *)firmware->id);
+       strncpy(qe_firmware_info.id, (char *)firmware->id, 62);
        qe_firmware_info.extended_modes = firmware->extended_modes;
        memcpy(qe_firmware_info.vtraps, firmware->vtraps,
                sizeof(firmware->vtraps));
@@ -470,7 +490,11 @@ int u_qe_upload_firmware(const struct qe_firmware *firmware)
        size_t length;
        const struct qe_header *hdr;
 #ifdef CONFIG_DEEP_SLEEP
+#ifdef CONFIG_LS102XA
+       struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+#else
        ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#endif
 #endif
        if (!firmware) {
                printf("Invalid address\n");
@@ -569,6 +593,76 @@ int u_qe_upload_firmware(const struct qe_firmware *firmware)
 }
 #endif
 
+#ifdef CONFIG_U_QE
+int u_qe_firmware_resume(const struct qe_firmware *firmware, qe_map_t *qe_immrr)
+{
+       unsigned int i;
+       unsigned int j;
+       const struct qe_header *hdr;
+       const u32 *code;
+#ifdef CONFIG_DEEP_SLEEP
+#ifdef CONFIG_PPC
+       ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#else
+       struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+#endif
+#endif
+
+       if (!firmware)
+               return -EINVAL;
+
+       hdr = &firmware->header;
+
+       /* Check the magic */
+       if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
+           (hdr->magic[2] != 'F')) {
+#ifdef CONFIG_DEEP_SLEEP
+               setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE);
+#endif
+               return -EPERM;
+       }
+
+       /*
+        * If the microcode calls for it, split the I-RAM.
+        */
+       if (!firmware->split) {
+               out_be16(&qe_immrr->cp.cercr,
+                        in_be16(&qe_immrr->cp.cercr) | QE_CP_CERCR_CIR);
+       }
+
+       /* Loop through each microcode. */
+       for (i = 0; i < firmware->count; i++) {
+               const struct qe_microcode *ucode = &firmware->microcode[i];
+
+               /* Upload a microcode if it's present */
+               if (!ucode->code_offset)
+                       return 0;
+
+               code = (const void *)firmware + be32_to_cpu(ucode->code_offset);
+
+               /* Use auto-increment */
+               out_be32(&qe_immrr->iram.iadd, be32_to_cpu(ucode->iram_offset) |
+                       QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR);
+
+               for (i = 0; i < be32_to_cpu(ucode->count); i++)
+                       out_be32(&qe_immrr->iram.idata, be32_to_cpu(code[i]));
+
+               /* Program the traps for this processor */
+               for (j = 0; j < 16; j++) {
+                       u32 trap = be32_to_cpu(ucode->traps[j]);
+
+                       if (trap)
+                               out_be32(&qe_immrr->rsp[i].tibcr[j], trap);
+               }
+
+               /* Enable traps */
+               out_be32(&qe_immrr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
+       }
+
+       return 0;
+}
+#endif
+
 struct qe_firmware_info *qe_get_firmware_info(void)
 {
        return qe_firmware_uploaded ? &qe_firmware_info : NULL;