arch/arm/dts: Add Turris Omnia device tree

[u-boot] / drivers / ram / bmips_ram.c

diff --git a/drivers/ram/bmips_ram.c b/drivers/ram/bmips_ram.c
index d0f7cd737688868ddeefd415cd5941506b896e66..3f9d9a8566155b9f7e5db21b776404dc8715d1e7 100644 (file)
--- a/drivers/ram/bmips_ram.c
+++ b/drivers/ram/bmips_ram.c
@@ -9,10 +9,20 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <errno.h>
 #include <ram.h>
 #include <asm/io.h>
-#include <dm/device.h>
+
+#define SDRAM_CFG_REG          0x0
+#define SDRAM_CFG_COL_SHIFT    4
+#define SDRAM_CFG_COL_MASK     (0x3 << SDRAM_CFG_COL_SHIFT)
+#define SDRAM_CFG_ROW_SHIFT    6
+#define SDRAM_CFG_ROW_MASK     (0x3 << SDRAM_CFG_ROW_SHIFT)
+#define SDRAM_CFG_32B_SHIFT    10
+#define SDRAM_CFG_32B_MASK     (1 << SDRAM_CFG_32B_SHIFT)
+#define SDRAM_CFG_BANK_SHIFT   13
+#define SDRAM_CFG_BANK_MASK    (1 << SDRAM_CFG_BANK_SHIFT)
 
 #define MEMC_CFG_REG           0x4
 #define MEMC_CFG_32B_SHIFT     1
@@ -40,24 +50,41 @@ static ulong bcm6328_get_ram_size(struct bmips_ram_priv *priv)
        return readl_be(priv->regs + DDR_CSEND_REG) << 24;
 }
 
+static ulong bmips_dram_size(unsigned int cols, unsigned int rows,
+                            unsigned int is_32b, unsigned int banks)
+{
+       rows += 11; /* 0 => 11 address bits ... 2 => 13 address bits */
+       cols += 8; /* 0 => 8 address bits ... 2 => 10 address bits */
+       is_32b += 1;
+
+       return 1 << (cols + rows + is_32b + banks);
+}
+
+static ulong bcm6338_get_ram_size(struct bmips_ram_priv *priv)
+{
+       unsigned int cols = 0, rows = 0, is_32b = 0, banks = 0;
+       u32 val;
+
+       val = readl_be(priv->regs + SDRAM_CFG_REG);
+       rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT;
+       cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT;
+       is_32b = (val & SDRAM_CFG_32B_MASK) ? 1 : 0;
+       banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
+
+       return bmips_dram_size(cols, rows, is_32b, banks);
+}
+
 static ulong bcm6358_get_ram_size(struct bmips_ram_priv *priv)
 {
-       unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
+       unsigned int cols = 0, rows = 0, is_32b = 0;
        u32 val;
 
        val = readl_be(priv->regs + MEMC_CFG_REG);
        rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
        cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
-       is_32bits = (val & MEMC_CFG_32B_MASK) ? 0 : 1;
-       banks = 2;
-
-       /* 0 => 11 address bits ... 2 => 13 address bits */
-       rows += 11;
+       is_32b = (val & MEMC_CFG_32B_MASK) ? 0 : 1;
 
-       /* 0 => 8 address bits ... 2 => 10 address bits */
-       cols += 8;
-
-       return 1 << (cols + rows + (is_32bits + 1) + banks);
+       return bmips_dram_size(cols, rows, is_32b, 2);
 }
 
 static int bmips_ram_get_info(struct udevice *dev, struct ram_info *info)
@@ -79,6 +106,10 @@ static const struct bmips_ram_hw bmips_ram_bcm6328 = {
        .get_ram_size = bcm6328_get_ram_size,
 };
 
+static const struct bmips_ram_hw bmips_ram_bcm6338 = {
+       .get_ram_size = bcm6338_get_ram_size,
+};
+
 static const struct bmips_ram_hw bmips_ram_bcm6358 = {
        .get_ram_size = bcm6358_get_ram_size,
 };
@@ -87,6 +118,9 @@ static const struct udevice_id bmips_ram_ids[] = {
        {
                .compatible = "brcm,bcm6328-mc",
                .data = (ulong)&bmips_ram_bcm6328,
+       }, {
+               .compatible = "brcm,bcm6338-mc",
+               .data = (ulong)&bmips_ram_bcm6338,
        }, {
                .compatible = "brcm,bcm6358-mc",
                .data = (ulong)&bmips_ram_bcm6358,
@@ -101,7 +135,7 @@ static int bmips_ram_probe(struct udevice *dev)
        fdt_addr_t addr;
        fdt_size_t size;
 
-       addr = dev_get_addr_size_index(dev, 0, &size);
+       addr = devfdt_get_addr_size_index(dev, 0, &size);
        if (addr == FDT_ADDR_T_NONE)
                return -EINVAL;