]> git.sur5r.net Git - u-boot/blobdiff - drivers/ram/stm32_sdram.c
Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTR
[u-boot] / drivers / ram / stm32_sdram.c
index 6fb89fbe3d65770fea2757dbdc7dc60d85d6c6a0..62282c613860e244fd8d7c88c8d015e139eb1bfe 100644 (file)
@@ -1,6 +1,6 @@
 /*
- * (C) Copyright 2017
- * Vikas Manocha, <vikas.manocha@st.com>
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
@@ -11,7 +11,8 @@
 #include <ram.h>
 #include <asm/io.h>
 
-DECLARE_GLOBAL_DATA_PTR;
+#define MEM_MODE_MASK  GENMASK(2, 0)
+#define NOT_FOUND      0xff
 
 struct stm32_fmc_regs {
        /* 0x0 */
@@ -54,6 +55,12 @@ struct stm32_fmc_regs {
        u32 sdsr;       /* SDRAM Status register */
 };
 
+/*
+ * NOR/PSRAM Control register BCR1
+ * FMC controller Enable, only availabe for H7
+ */
+#define FMC_BCR1_FMCEN         BIT(31)
+
 /* Control register SDCR */
 #define FMC_SDCR_RPIPE_SHIFT   13      /* RPIPE bit shift */
 #define FMC_SDCR_RBURST_SHIFT  12      /* RBURST bit shift */
@@ -123,6 +130,11 @@ enum stm32_fmc_bank {
        MAX_SDRAM_BANK,
 };
 
+enum stm32_fmc_family {
+       STM32F7_FMC,
+       STM32H7_FMC,
+};
+
 struct bank_params {
        struct stm32_sdram_control *sdram_control;
        struct stm32_sdram_timing *sdram_timing;
@@ -134,6 +146,7 @@ struct stm32_sdram_params {
        struct stm32_fmc_regs *base;
        u8 no_sdram_banks;
        struct bank_params bank_params[MAX_SDRAM_BANK];
+       enum stm32_fmc_family family;
 };
 
 #define SDRAM_MODE_BL_SHIFT    0
@@ -151,6 +164,10 @@ int stm32_sdram_init(struct udevice *dev)
        u32 ref_count;
        u8 i;
 
+       /* disable the FMC controller */
+       if (params->family == STM32H7_FMC)
+               clrbits_le32(&regs->bcr1, FMC_BCR1_FMCEN);
+
        for (i = 0; i < params->no_sdram_banks; i++) {
                control = params->bank_params[i].sdram_control;
                timing = params->bank_params[i].sdram_timing;
@@ -193,6 +210,7 @@ int stm32_sdram_init(struct udevice *dev)
                                | timing->txsr << FMC_SDTR_TXSR_SHIFT
                                | timing->tmrd << FMC_SDTR_TMRD_SHIFT,
                                &regs->sdtr2);
+
                if (target_bank == SDRAM_BANK1)
                        ctb = FMC_SDCMR_BANK_1;
                else
@@ -225,6 +243,10 @@ int stm32_sdram_init(struct udevice *dev)
                writel(ref_count << 1, &regs->sdrtr);
        }
 
+       /* enable the FMC controller */
+       if (params->family == STM32H7_FMC)
+               setbits_le32(&regs->bcr1, FMC_BCR1_FMCEN);
+
        return 0;
 }
 
@@ -232,16 +254,38 @@ static int stm32_fmc_ofdata_to_platdata(struct udevice *dev)
 {
        struct stm32_sdram_params *params = dev_get_platdata(dev);
        struct bank_params *bank_params;
+       struct ofnode_phandle_args args;
+       u32 *syscfg_base;
+       u32 mem_remap;
        ofnode bank_node;
        char *bank_name;
        u8 bank = 0;
+       int ret;
+
+       mem_remap = dev_read_u32_default(dev, "st,mem_remap", NOT_FOUND);
+       if (mem_remap != NOT_FOUND) {
+               ret = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
+                                                &args);
+               if (ret) {
+                       debug("%s: can't find syscon device (%d)\n", __func__,
+                             ret);
+                       return ret;
+               }
+
+               syscfg_base = (u32 *)ofnode_get_addr(args.node);
+
+               /* set memory mapping selection */
+               clrsetbits_le32(syscfg_base, MEM_MODE_MASK, mem_remap);
+       } else {
+               debug("%s: cannot find st,mem_remap property\n", __func__);
+       }
 
        dev_for_each_subnode(bank_node, dev) {
                /* extract the bank index from DT */
                bank_name = (char *)ofnode_get_name(bank_node);
                strsep(&bank_name, "@");
                if (!bank_name) {
-                       error("missing sdram bank index");
+                       pr_err("missing sdram bank index");
                        return -EINVAL;
                }
 
@@ -250,7 +294,7 @@ static int stm32_fmc_ofdata_to_platdata(struct udevice *dev)
                               (long unsigned int *)&bank_params->target_bank);
 
                if (bank_params->target_bank >= MAX_SDRAM_BANK) {
-                       error("Found bank %d , but only bank 0 and 1 are supported",
+                       pr_err("Found bank %d , but only bank 0 and 1 are supported",
                              bank_params->target_bank);
                        return -EINVAL;
                }
@@ -264,7 +308,7 @@ static int stm32_fmc_ofdata_to_platdata(struct udevice *dev)
                                                  sizeof(struct stm32_sdram_control));
 
                if (!params->bank_params[bank].sdram_control) {
-                       error("st,sdram-control not found for %s",
+                       pr_err("st,sdram-control not found for %s",
                              ofnode_get_name(bank_node));
                        return -EINVAL;
                }
@@ -277,7 +321,7 @@ static int stm32_fmc_ofdata_to_platdata(struct udevice *dev)
                                                  sizeof(struct stm32_sdram_timing));
 
                if (!params->bank_params[bank].sdram_timing) {
-                       error("st,sdram-timing not found for %s",
+                       pr_err("st,sdram-timing not found for %s",
                              ofnode_get_name(bank_node));
                        return -EINVAL;
                }
@@ -305,6 +349,7 @@ static int stm32_fmc_probe(struct udevice *dev)
                return -EINVAL;
 
        params->base = (struct stm32_fmc_regs *)addr;
+       params->family = dev_get_driver_data(dev);
 
 #ifdef CONFIG_CLK
        struct clk clk;
@@ -337,7 +382,8 @@ static struct ram_ops stm32_fmc_ops = {
 };
 
 static const struct udevice_id stm32_fmc_ids[] = {
-       { .compatible = "st,stm32-fmc" },
+       { .compatible = "st,stm32-fmc", .data = STM32F7_FMC },
+       { .compatible = "st,stm32h7-fmc", .data = STM32H7_FMC },
        { }
 };