Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze

[u-boot] / drivers / serial / serial_pl01x.c

diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c
index 2a6b61d40da54ed2d682504bcca3988767b32baf..2124161734c0a40f4baf1a86de933be307e4e467 100644 (file)
--- a/drivers/serial/serial_pl01x.c
+++ b/drivers/serial/serial_pl01x.c
@@ -72,22 +72,19 @@ static int pl01x_tstc(struct pl01x_regs *regs)
 static int pl01x_generic_serial_init(struct pl01x_regs *regs,
                                     enum pl01x_type type)
 {
+       switch (type) {
+       case TYPE_PL010:
+               /* disable everything */
+               writel(0, &regs->pl010_cr);
+               break;
+       case TYPE_PL011:
 #ifdef CONFIG_PL011_SERIAL_FLUSH_ON_INIT
-       if (type == TYPE_PL011) {
                /* Empty RX fifo if necessary */
                if (readl(&regs->pl011_cr) & UART_PL011_CR_UARTEN) {
                        while (!(readl(&regs->fr) & UART_PL01x_FR_RXFE))
                                readl(&regs->dr);
                }
-       }
 #endif
-
-       switch (type) {
-       case TYPE_PL010:
-               /* disable everything */
-               writel(0, &regs->pl010_cr);
-               break;
-       case TYPE_PL011:
                /* disable everything */
                writel(0, &regs->pl011_cr);
                break;
@@ -98,7 +95,7 @@ static int pl01x_generic_serial_init(struct pl01x_regs *regs,
        return 0;
 }
 
-static int set_line_control(struct pl01x_regs *regs)
+static int pl011_set_line_control(struct pl01x_regs *regs)
 {
        unsigned int lcr;
        /*
@@ -132,6 +129,9 @@ static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
        case TYPE_PL010: {
                unsigned int divisor;
 
+               /* disable everything */
+               writel(0, &regs->pl010_cr);
+
                switch (baudrate) {
                case 9600:
                        divisor = UART_PL010_BAUD_9600;
@@ -155,6 +155,12 @@ static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
                writel((divisor & 0xf00) >> 8, &regs->pl010_lcrm);
                writel(divisor & 0xff, &regs->pl010_lcrl);
 
+               /*
+                * Set line control for the PL010 to be 8 bits, 1 stop bit,
+                * no parity, fifo enabled
+                */
+               writel(UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN,
+                      &regs->pl010_lcrh);
                /* Finally, enable the UART */
                writel(UART_PL010_CR_UARTEN, &regs->pl010_cr);
                break;
@@ -181,7 +187,7 @@ static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
                writel(divider, &regs->pl011_ibrd);
                writel(fraction, &regs->pl011_fbrd);
 
-               set_line_control(regs);
+               pl011_set_line_control(regs);
                /* Finally, enable the UART */
                writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE |
                       UART_PL011_CR_RXE | UART_PL011_CR_RTS, &regs->pl011_cr);
@@ -351,6 +357,7 @@ U_BOOT_DRIVER(serial_pl01x) = {
        .probe = pl01x_serial_probe,
        .ops    = &pl01x_serial_ops,
        .flags = DM_FLAG_PRE_RELOC,
+       .priv_auto_alloc_size = sizeof(struct pl01x_priv),
 };
 
 #endif