Merge tag 'xilinx-for-v2018.07-2' of git://www.denx.de/git/u-boot-microblaze

[u-boot] / drivers / serial / serial_rockchip.c

diff --git a/drivers/serial/serial_rockchip.c b/drivers/serial/serial_rockchip.c
index 6bac95a414cec02082979978ff1dfed84f1ef515..35fefd74c696348577df53b3064a3196017dd7ce 100644 (file)
--- a/drivers/serial/serial_rockchip.c
+++ b/drivers/serial/serial_rockchip.c
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (c) 2015 Google, Inc
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -12,12 +11,19 @@
 #include <serial.h>
 #include <asm/arch/clock.h>
 
+#if defined(CONFIG_ROCKCHIP_RK3188)
+struct rockchip_uart_platdata {
+       struct dtd_rockchip_rk3188_uart dtplat;
+       struct ns16550_platdata plat;
+};
+struct dtd_rockchip_rk3188_uart *dtplat, s_dtplat;
+#elif defined(CONFIG_ROCKCHIP_RK3288)
 struct rockchip_uart_platdata {
        struct dtd_rockchip_rk3288_uart dtplat;
        struct ns16550_platdata plat;
 };
-
 struct dtd_rockchip_rk3288_uart *dtplat, s_dtplat;
+#endif
 
 static int rockchip_serial_probe(struct udevice *dev)
 {
@@ -27,11 +33,22 @@ static int rockchip_serial_probe(struct udevice *dev)
        plat->plat.base = plat->dtplat.reg[0];
        plat->plat.reg_shift = plat->dtplat.reg_shift;
        plat->plat.clock = plat->dtplat.clock_frequency;
+       plat->plat.fcr = UART_FCR_DEFVAL;
        dev->platdata = &plat->plat;
 
        return ns16550_serial_probe(dev);
 }
 
+U_BOOT_DRIVER(rockchip_rk3188_uart) = {
+       .name   = "rockchip_rk3188_uart",
+       .id     = UCLASS_SERIAL,
+       .priv_auto_alloc_size = sizeof(struct NS16550),
+       .platdata_auto_alloc_size = sizeof(struct rockchip_uart_platdata),
+       .probe  = rockchip_serial_probe,
+       .ops    = &ns16550_serial_ops,
+       .flags  = DM_FLAG_PRE_RELOC,
+};
+
 U_BOOT_DRIVER(rockchip_rk3288_uart) = {
        .name   = "rockchip_rk3288_uart",
        .id     = UCLASS_SERIAL,