arm: stm32: add new architecture for STM32MP family

[u-boot] / drivers / serial / serial_sh.c

diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c
index 087785f9a249ef7151456ae46b9d09d53db70d54..a17698f90ee89a3cbe39b3a2f1d6a70afdcbdd5f 100644 (file)
--- a/drivers/serial/serial_sh.c
+++ b/drivers/serial/serial_sh.c
@@ -149,7 +149,7 @@ static int sh_serial_getc_generic(struct uart_port *port)
        return ch;
 }
 
-#ifdef CONFIG_DM_SERIAL
+#if CONFIG_IS_ENABLED(DM_SERIAL)
 
 static int sh_serial_pending(struct udevice *dev, bool input)
 {
@@ -204,7 +204,7 @@ static const struct dm_serial_ops sh_serial_ops = {
        .setbrg = sh_serial_setbrg,
 };
 
-#ifdef CONFIG_OF_CONTROL
+#if CONFIG_IS_ENABLED(OF_CONTROL)
 static const struct udevice_id sh_serial_id[] ={
        {.compatible = "renesas,sci", .data = PORT_SCI},
        {.compatible = "renesas,scif", .data = PORT_SCIF},
@@ -219,18 +219,21 @@ static int sh_serial_ofdata_to_platdata(struct udevice *dev)
        fdt_addr_t addr;
        int ret;
 
-       addr = fdtdec_get_addr(gd->fdt_blob, dev_of_offset(dev), "reg");
-       if (addr == FDT_ADDR_T_NONE)
+       addr = devfdt_get_addr(dev);
+       if (!addr)
                return -EINVAL;
 
        plat->base = addr;
 
        ret = clk_get_by_name(dev, "fck", &sh_serial_clk);
-       if (!ret)
-               plat->clk = clk_get_rate(&sh_serial_clk);
-       else
+       if (!ret) {
+               ret = clk_enable(&sh_serial_clk);
+               if (!ret)
+                       plat->clk = clk_get_rate(&sh_serial_clk);
+       } else {
                plat->clk = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
                                           "clock", 1);
+       }
 
        plat->type = dev_get_driver_data(dev);
        return 0;