]> git.sur5r.net Git - u-boot/blobdiff - drivers/serial/serial_sh.c
bcm283x_pl011: Flush RX queue after setting baud rate
[u-boot] / drivers / serial / serial_sh.c
index ef7cf0f26c84673799b79d08f66ceb777e568ffa..a17698f90ee89a3cbe39b3a2f1d6a70afdcbdd5f 100644 (file)
@@ -9,6 +9,7 @@
 
 #include <common.h>
 #include <errno.h>
+#include <clk.h>
 #include <dm.h>
 #include <asm/io.h>
 #include <asm/processor.h>
@@ -148,7 +149,7 @@ static int sh_serial_getc_generic(struct uart_port *port)
        return ch;
 }
 
-#ifdef CONFIG_DM_SERIAL
+#if CONFIG_IS_ENABLED(DM_SERIAL)
 
 static int sh_serial_pending(struct udevice *dev, bool input)
 {
@@ -203,7 +204,7 @@ static const struct dm_serial_ops sh_serial_ops = {
        .setbrg = sh_serial_setbrg,
 };
 
-#ifdef CONFIG_OF_CONTROL
+#if CONFIG_IS_ENABLED(OF_CONTROL)
 static const struct udevice_id sh_serial_id[] ={
        {.compatible = "renesas,sci", .data = PORT_SCI},
        {.compatible = "renesas,scif", .data = PORT_SCIF},
@@ -214,14 +215,26 @@ static const struct udevice_id sh_serial_id[] ={
 static int sh_serial_ofdata_to_platdata(struct udevice *dev)
 {
        struct sh_serial_platdata *plat = dev_get_platdata(dev);
+       struct clk sh_serial_clk;
        fdt_addr_t addr;
+       int ret;
 
-       addr = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg");
-       if (addr == FDT_ADDR_T_NONE)
+       addr = devfdt_get_addr(dev);
+       if (!addr)
                return -EINVAL;
 
        plat->base = addr;
-       plat->clk = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "clock", 1);
+
+       ret = clk_get_by_name(dev, "fck", &sh_serial_clk);
+       if (!ret) {
+               ret = clk_enable(&sh_serial_clk);
+               if (!ret)
+                       plat->clk = clk_get_rate(&sh_serial_clk);
+       } else {
+               plat->clk = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+                                          "clock", 1);
+       }
+
        plat->type = dev_get_driver_data(dev);
        return 0;
 }