Merge branch 'elf_reloc'

[u-boot] / drivers / serial / serial_sh.c

diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c
index 1d76a194a5fcdb2078978c47743eb489eb4e2f69..bfdb2ce77a3b9baea4e1e4f3a1182458102f57b0 100644 (file)
--- a/drivers/serial/serial_sh.c
+++ b/drivers/serial/serial_sh.c
@@ -18,6 +18,7 @@
  */
 
 #include <common.h>
+#include <asm/io.h>
 #include <asm/processor.h>
 
 #if defined(CONFIG_CONS_SCIF0)
@@ -49,7 +50,7 @@
 # define SCFRDR        (vu_char  *)(SCIF_BASE + 0x24)
 #else
 # define SCFTDR (vu_char  *)(SCIF_BASE + 0xC)
-# define SCFSR         (vu_short *)(SCIF_BASE + 0x10)
+# define SCFSR (vu_short *)(SCIF_BASE + 0x10)
 # define SCFRDR (vu_char  *)(SCIF_BASE + 0x14)
 #endif
 
@@ -64,7 +65,7 @@
 #elif defined(CONFIG_CPU_SH7763)
 # if defined(CONFIG_CONS_SCIF2)
 # define SCSPTR        (vu_short *)(SCIF_BASE + 0x20)
-# define SCLSR         (vu_short *)(SCIF_BASE + 0x24)
+# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
 # define LSR_ORER      1
 # define FIFOLEVEL_MASK        0x1F
 # else
@@ -90,7 +91,7 @@
        defined(CONFIG_CPU_SH7722) || \
        defined(CONFIG_CPU_SH7203)
 # define SCSPTR        (vu_short *)(SCIF_BASE + 0x20)
-# define SCLSR         (vu_short *)(SCIF_BASE + 0x24)
+# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
 # define LSR_ORER      1
 # define FIFOLEVEL_MASK        0x1F
 #elif defined(CONFIG_CPU_SH7720)
@@ -106,42 +107,43 @@
 
 /* SCBRR register value setting */
 #if defined(CONFIG_CPU_SH7720)
-# define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
+# define SCBRR_VALUE(bps, clk) (((clk * 2) + 16 * bps) / (32 * bps) - 1)
 #elif defined(CONFIG_CPU_SH7723) && defined(CONFIG_SCIF_A)
 /* SH7723 SCIFA use bus clock. So clock *2 */
-# define SCBRR_VALUE(bps, clk) (((clk*2*2)+16*bps)/(32*bps)-1)
+# define SCBRR_VALUE(bps, clk) (((clk * 2 * 2) + 16 * bps) / (32 * bps) - 1)
 #else /* Generic SuperH */
-# define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
+# define SCBRR_VALUE(bps, clk) ((clk + 16 * bps) / (32 * bps) - 1)
 #endif
 
-#define SCR_RE                 (1 << 4)
-#define SCR_TE                 (1 << 5)
+#define SCR_RE         (1 << 4)
+#define SCR_TE         (1 << 5)
 #define FCR_RFRST      (1 << 1)        /* RFCL */
 #define FCR_TFRST      (1 << 2)        /* TFCL */
-#define FSR_DR         (1 << 0)
-#define FSR_RDF        (1 << 1)
-#define FSR_FER        (1 << 3)
-#define FSR_BRK        (1 << 4)
-#define FSR_FER        (1 << 3)
-#define FSR_TEND       (1 << 6)
-#define FSR_ER         (1 << 7)
+#define FSR_DR         (1 << 0)
+#define FSR_RDF                (1 << 1)
+#define FSR_FER                (1 << 3)
+#define FSR_BRK                (1 << 4)
+#define FSR_FER                (1 << 3)
+#define FSR_TEND       (1 << 6)
+#define FSR_ER         (1 << 7)
 
 /*----------------------------------------------------------------------*/
 
 void serial_setbrg(void)
 {
        DECLARE_GLOBAL_DATA_PTR;
-       *SCBRR = SCBRR_VALUE(gd->baudrate, CONFIG_SYS_CLK_FREQ);
+
+       writeb(SCBRR_VALUE(gd->baudrate, CONFIG_SYS_CLK_FREQ), SCBRR);
 }
 
 int serial_init(void)
 {
-       *SCSCR = (SCR_RE | SCR_TE);
-       *SCSMR = 0;
-       *SCSMR = 0;
-       *SCFCR = (FCR_RFRST | FCR_TFRST);
-       *SCFCR;
-       *SCFCR = 0;
+       writew((SCR_RE | SCR_TE), SCSCR);
+       writew(0, SCSMR);
+       writew(0, SCSMR);
+       writew((FCR_RFRST | FCR_TFRST), SCFCR);
+       readw(SCFCR);
+       writew(0, SCFCR);
 
        serial_setbrg();
        return 0;
@@ -150,9 +152,9 @@ int serial_init(void)
 static int serial_rx_fifo_level(void)
 {
 #if defined(SCRFDR)
-       return (*SCRFDR >> 0) & FIFOLEVEL_MASK;
+       return (readw(SCRFDR) >> 0) & FIFOLEVEL_MASK;
 #else
-       return (*SCFDR >> 0) & FIFOLEVEL_MASK;
+       return (readw(SCFDR) >> 0) & FIFOLEVEL_MASK;
 #endif
 }
 
@@ -161,15 +163,15 @@ void serial_raw_putc(const char c)
        unsigned int fsr_bits_to_clear;
 
        while (1) {
-               if (*SCFSR & FSR_TEND) {        /* Tx fifo is empty */
+               if (readw(SCFSR) & FSR_TEND) { /* Tx fifo is empty */
                        fsr_bits_to_clear = FSR_TEND;
                        break;
                }
        }
 
-       *SCFTDR = c;
+       writeb(c, SCFTDR);
        if (fsr_bits_to_clear != 0)
-               *SCFSR &= ~fsr_bits_to_clear;
+               writew(readw(SCFSR) & ~fsr_bits_to_clear, SCFSR);
 }
 
 void serial_putc(const char c)
@@ -191,26 +193,25 @@ int serial_tstc(void)
        return serial_rx_fifo_level() ? 1 : 0;
 }
 
-#define FSR_ERR_CLEAR   0x0063
-#define RDRF_CLEAR      0x00fc
+#define FSR_ERR_CLEAR  0x0063
+#define RDRF_CLEAR             0x00fc
 void handle_error(void)
 {
-
-       (void)*SCFSR;
-       *SCFSR = FSR_ERR_CLEAR;
-       (void)*SCLSR;
-       *SCLSR = 0x00;
+       readw(SCFSR);
+       writew(FSR_ERR_CLEAR, SCFSR);
+       readw(SCLSR);
+       writew(0x00, SCLSR);
 }
 
 int serial_getc_check(void)
 {
        unsigned short status;
 
-       status = *SCFSR;
+       status = readw(SCFSR);
 
        if (status & (FSR_FER | FSR_ER | FSR_BRK))
                handle_error();
-       if (*SCLSR & LSR_ORER)
+       if (readw(SCLSR) & LSR_ORER)
                handle_error();
        return status & (FSR_DR | FSR_RDF);
 }
@@ -223,15 +224,15 @@ int serial_getc(void)
        while (!serial_getc_check())
                ;
 
-       ch = *SCFRDR;
-       status = *SCFSR;
+       ch = readb(SCFRDR);
+       status = readw(SCFSR);
 
-       *SCFSR = RDRF_CLEAR;
+       writew(RDRF_CLEAR, SCFSR);
 
        if (status & (FSR_FER | FSR_FER | FSR_ER | FSR_BRK))
                handle_error();
 
-       if (*SCLSR & LSR_ORER)
+       if (readw(SCLSR) & LSR_ORER)
                handle_error();
 
        return ch;