i.MX28: Add cache support to MXS NAND driver

[u-boot] / drivers / serial / serial_sh.h

diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h
index 54e94e5bf1134783beaf0299ec95ecf7c956b5ca..0b3e779c8e53915c7bb5a305578e36f1dff6fc2e 100644 (file)
--- a/drivers/serial/serial_sh.h
+++ b/drivers/serial/serial_sh.h
@@ -177,7 +177,8 @@ struct uart_port {
 #elif defined(CONFIG_CPU_SH7201) || \
        defined(CONFIG_CPU_SH7203) || \
        defined(CONFIG_CPU_SH7206) || \
-       defined(CONFIG_CPU_SH7263)
+       defined(CONFIG_CPU_SH7263) || \
+       defined(CONFIG_CPU_SH7264)
 # define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
 # define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
 # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
@@ -675,14 +676,14 @@ static inline int sci_rxd_in(struct uart_port *port)
 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
 #elif defined(CONFIG_CPU_SH7723) ||\
        defined(CONFIG_CPU_SH7724)
-static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
+static inline int scbrr_calc(struct uart_port port, int bps, int clk)
 {
-       if (port->type == PORT_SCIF)
+       if (port.type == PORT_SCIF)
                return (clk+16*bps)/(32*bps)-1;
        else
                return ((clk*2)+16*bps)/(16*bps)-1;
 }
-#define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
+#define SCBRR_VALUE(bps, clk) scbrr_calc(sh_sci, bps, clk)
 #elif defined(__H8300H__) || defined(__H8300S__)
 #define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
 #else /* Generic SH */