Merge branch 'master' of git://git.denx.de/u-boot-i2c

[u-boot] / drivers / serial / serial_stm32.c

diff --git a/drivers/serial/serial_stm32.c b/drivers/serial/serial_stm32.c
index 724d6f967246d35f48990f84523aa71c076bea56..f26234549c3e18ee18b7d532ac707c379dd83067 100644 (file)
--- a/drivers/serial/serial_stm32.c
+++ b/drivers/serial/serial_stm32.c
@@ -47,6 +47,45 @@ static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
        return 0;
 }
 
+static int stm32_serial_setparity(struct udevice *dev, enum serial_par parity)
+{
+       struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
+       bool stm32f4 = plat->uart_info->stm32f4;
+       u8 uart_enable_bit = plat->uart_info->uart_enable_bit;
+       u32 cr1 = plat->base + CR1_OFFSET(stm32f4);
+       u32 config = 0;
+
+       if (stm32f4)
+               return -EINVAL; /* not supported in driver*/
+
+       clrbits_le32(cr1, USART_CR1_RE | USART_CR1_TE | BIT(uart_enable_bit));
+       /* update usart configuration (uart need to be disable)
+        * PCE: parity check control
+        * PS : '0' : Even / '1' : Odd
+        * M[1:0] = '00' : 8 Data bits
+        * M[1:0] = '01' : 9 Data bits with parity
+        */
+       switch (parity) {
+       default:
+       case SERIAL_PAR_NONE:
+               config = 0;
+               break;
+       case SERIAL_PAR_ODD:
+               config = USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0;
+               break;
+       case SERIAL_PAR_EVEN:
+               config = USART_CR1_PCE | USART_CR1_M0;
+               break;
+       }
+       clrsetbits_le32(cr1,
+                       USART_CR1_PCE | USART_CR1_PS | USART_CR1_M1 |
+                       USART_CR1_M0,
+                       config);
+       setbits_le32(cr1, USART_CR1_RE | USART_CR1_TE | BIT(uart_enable_bit));
+
+       return 0;
+}
+
 static int stm32_serial_getc(struct udevice *dev)
 {
        struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
@@ -54,12 +93,13 @@ static int stm32_serial_getc(struct udevice *dev)
        fdt_addr_t base = plat->base;
        u32 isr = readl(base + ISR_OFFSET(stm32f4));
 
-       if ((isr & USART_ISR_FLAG_RXNE) == 0)
+       if ((isr & USART_ISR_RXNE) == 0)
                return -EAGAIN;
 
-       if (isr & USART_ISR_FLAG_ORE) {
+       if (isr & (USART_ISR_PE | USART_ISR_ORE)) {
                if (!stm32f4)
-                       setbits_le32(base + ICR_OFFSET, USART_ICR_OREF);
+                       setbits_le32(base + ICR_OFFSET,
+                                    USART_ICR_PCECF | USART_ICR_ORECF);
                else
                        readl(base + RDR_OFFSET(stm32f4));
                return -EIO;
@@ -74,7 +114,7 @@ static int _stm32_serial_putc(fdt_addr_t base,
 {
        bool stm32f4 = uart_info->stm32f4;
 
-       if ((readl(base + ISR_OFFSET(stm32f4)) & USART_ISR_FLAG_TXE) == 0)
+       if ((readl(base + ISR_OFFSET(stm32f4)) & USART_ISR_TXE) == 0)
                return -EAGAIN;
 
        writel(c, base + TDR_OFFSET(stm32f4));
@@ -97,10 +137,10 @@ static int stm32_serial_pending(struct udevice *dev, bool input)
 
        if (input)
                return readl(base + ISR_OFFSET(stm32f4)) &
-                       USART_ISR_FLAG_RXNE ? 1 : 0;
+                       USART_ISR_RXNE ? 1 : 0;
        else
                return readl(base + ISR_OFFSET(stm32f4)) &
-                       USART_ISR_FLAG_TXE ? 0 : 1;
+                       USART_ISR_TXE ? 0 : 1;
 }
 
 static void _stm32_serial_init(fdt_addr_t base,
@@ -170,6 +210,7 @@ static const struct dm_serial_ops stm32_serial_ops = {
        .pending = stm32_serial_pending,
        .getc = stm32_serial_getc,
        .setbrg = stm32_serial_setbrg,
+       .setparity = stm32_serial_setparity
 };
 
 U_BOOT_DRIVER(serial_stm32) = {