Merge branch 'master' of git://git.denx.de/u-boot-sunxi

[u-boot] / drivers / serial / serial_zynq.c

diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c
index 4f6e7e442fa2288f5e4d502302f9c5ac3ad0c968..a191772ff0403240128475099c27d5609f661e54 100644 (file)
--- a/drivers/serial/serial_zynq.c
+++ b/drivers/serial/serial_zynq.c
@@ -1,8 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
  * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <clk.h>
@@ -15,19 +14,17 @@
 #include <asm/io.h>
 #include <linux/compiler.h>
 #include <serial.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/hardware.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define ZYNQ_UART_SR_TXEMPTY   (1 << 3) /* TX FIFO empty */
-#define ZYNQ_UART_SR_TXACTIVE  (1 << 11)  /* TX active */
-#define ZYNQ_UART_SR_RXEMPTY   0x00000002 /* RX FIFO empty */
+#define ZYNQ_UART_SR_TXACTIVE  BIT(11) /* TX active */
+#define ZYNQ_UART_SR_TXFULL    BIT(4) /* TX FIFO full */
+#define ZYNQ_UART_SR_RXEMPTY   BIT(1) /* RX FIFO empty */
 
-#define ZYNQ_UART_CR_TX_EN     0x00000010 /* TX enabled */
-#define ZYNQ_UART_CR_RX_EN     0x00000004 /* RX enabled */
-#define ZYNQ_UART_CR_TXRST     0x00000002 /* TX logic reset */
-#define ZYNQ_UART_CR_RXRST     0x00000001 /* RX logic reset */
+#define ZYNQ_UART_CR_TX_EN     BIT(4) /* TX enabled */
+#define ZYNQ_UART_CR_RX_EN     BIT(2) /* RX enabled */
+#define ZYNQ_UART_CR_TXRST     BIT(1) /* TX logic reset */
+#define ZYNQ_UART_CR_RXRST     BIT(0) /* RX logic reset */
 
 #define ZYNQ_UART_MR_PARITY_NONE       0x00000020  /* No parity mode */
 
@@ -98,7 +95,7 @@ static void _uart_zynq_serial_init(struct uart_zynq *regs)
 
 static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c)
 {
-       if (!(readl(&regs->channel_sts) & ZYNQ_UART_SR_TXEMPTY))
+       if (readl(&regs->channel_sts) & ZYNQ_UART_SR_TXFULL)
                return -EAGAIN;
 
        writel(c, &regs->tx_rx_fifo);
@@ -106,12 +103,11 @@ static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c)
        return 0;
 }
 
-int zynq_serial_setbrg(struct udevice *dev, int baudrate)
+static int zynq_serial_setbrg(struct udevice *dev, int baudrate)
 {
        struct zynq_uart_priv *priv = dev_get_priv(dev);
        unsigned long clock;
 
-#if defined(CONFIG_CLK) || defined(CONFIG_SPL_CLK)
        int ret;
        struct clk clk;
 
@@ -133,9 +129,7 @@ int zynq_serial_setbrg(struct udevice *dev, int baudrate)
                dev_err(dev, "failed to enable clock\n");
                return ret;
        }
-#else
-       clock = get_uart_clk(0);
-#endif
+
        _uart_zynq_serial_setbrg(priv->regs, clock, baudrate);
 
        return 0;
@@ -145,6 +139,10 @@ static int zynq_serial_probe(struct udevice *dev)
 {
        struct zynq_uart_priv *priv = dev_get_priv(dev);
 
+       /* No need to reinitialize the UART after relocation */
+       if (gd->flags & GD_FLG_RELOC)
+               return 0;
+
        _uart_zynq_serial_init(priv->regs);
 
        return 0;
@@ -183,7 +181,9 @@ static int zynq_serial_ofdata_to_platdata(struct udevice *dev)
 {
        struct zynq_uart_priv *priv = dev_get_priv(dev);
 
-       priv->regs = (struct uart_zynq *)dev_get_addr(dev);
+       priv->regs = (struct uart_zynq *)dev_read_addr(dev);
+       if (IS_ERR(priv->regs))
+               return PTR_ERR(priv->regs);
 
        return 0;
 }