Merge branch 'master' of git://git.denx.de/u-boot-nios

[u-boot] / drivers / spi / Kconfig

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 8ffb3c47cb84e51b22cafaad4bf33a08c535511b..7d7a9d0809493def7fa0fc38127509129cdcb713 100644 (file)
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -15,6 +15,14 @@ config DM_SPI
 
 if DM_SPI
 
+config ALTERA_SPI
+       bool "Altera SPI driver"
+       help
+         Enable the Altera SPI driver. This driver can be used to
+         access the SPI NOR flash on platforms embedding this Altera
+         IP core. Please find details on the "Embedded Peripherals IP
+         User Guide" of Altera.
+
 config CADENCE_QSPI
        bool "Cadence QSPI driver"
        help
@@ -58,6 +66,14 @@ config ICH_SPI
          access the SPI NOR flash on platforms embedding this Intel
          ICH IP core.
 
+config ROCKCHIP_SPI
+       bool "Rockchip SPI driver"
+       help
+         Enable the Rockchip SPI driver, used to access SPI NOR flash and
+         other SPI peripherals (such as the Chrome OS EC) on Rockchip SoCs.
+         This uses driver model and requires a device tree binding to
+         operate.
+
 config SANDBOX_SPI
        bool "Sandbox SPI driver"
        depends on SANDBOX && DM
@@ -100,6 +116,13 @@ config TEGRA20_SFLASH
          can be used to access the SPI NOR flash on platforms embedding this
          nVidia Tegra20 IP core.
 
+config TEGRA20_SLINK
+       bool "nVidia Tegra20/Tegra30 SLINK driver"
+       help
+         Enable the nVidia Tegra20/Tegra30 SLINK driver. This driver can
+         be used to access the SPI NOR flash on platforms embedding this
+         nVidia Tegra20/Tegra30 IP cores.
+
 config XILINX_SPI
        bool "Xilinx SPI driver"
        help
@@ -116,6 +139,15 @@ config ZYNQ_SPI
          access the SPI NOR flash on platforms embedding this Zynq
          SPI IP core.
 
+config ZYNQ_QSPI
+       bool "Zynq QSPI driver"
+       depends on ARCH_ZYNQ
+       help
+         Enable the Zynq Quad-SPI (QSPI) driver. This driver can be
+         used to access the SPI NOR flash on platforms embedding this
+         Zynq QSPI IP core. This IP is used to connect the flash in
+         4-bit qspi, 8-bit dual stacked and shared 4-bit dual parallel.
+
 endif # if DM_SPI
 
 config FSL_ESPI