sbc8641d: increase malloc pool size to a sane default

[u-boot] / drivers / spi / Kconfig

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index d5e688116d4c57bca4fa28318e5e8d6cee59efe7..8e04fce6f2ab10075f59ac53b5ec1c077b515905 100644 (file)
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -51,6 +51,21 @@ config FSL_QSPI
          used to access the SPI NOR flash on platforms embedding this
          Freescale IP core.
 
+config ICH_SPI
+       bool "Intel ICH SPI driver"
+       help
+         Enable the Intel ICH SPI driver. This driver can be used to
+         access the SPI NOR flash on platforms embedding this Intel
+         ICH IP core.
+
+config ROCKCHIP_SPI
+       bool "Rockchip SPI driver"
+       help
+         Enable the Rockchip SPI driver, used to access SPI NOR flash and
+         other SPI peripherals (such as the Chrome OS EC) on Rockchip SoCs.
+         This uses driver model and requires a device tree binding to
+         operate.
+
 config SANDBOX_SPI
        bool "Sandbox SPI driver"
        depends on SANDBOX && DM
@@ -76,6 +91,30 @@ config SANDBOX_SPI
                };
          };
 
+config TEGRA114_SPI
+       bool "nVidia Tegra114 SPI driver"
+       help
+         Enable the nVidia Tegra114 SPI driver. This driver can be used to
+         access the SPI NOR flash on platforms embedding this nVidia Tegra114
+         IP core.
+
+         This controller is different than the older SoCs SPI controller and
+         also register interface get changed with this controller.
+
+config TEGRA20_SFLASH
+       bool "nVidia Tegra20 Serial Flash controller driver"
+       help
+         Enable the nVidia Tegra20 Serial Flash controller driver. This driver
+         can be used to access the SPI NOR flash on platforms embedding this
+         nVidia Tegra20 IP core.
+
+config TEGRA20_SLINK
+       bool "nVidia Tegra20/Tegra30 SLINK driver"
+       help
+         Enable the nVidia Tegra20/Tegra30 SLINK driver. This driver can
+         be used to access the SPI NOR flash on platforms embedding this
+         nVidia Tegra20/Tegra30 IP cores.
+
 config XILINX_SPI
        bool "Xilinx SPI driver"
        help