(read_SPI_FLG(bss) &
~((!bss->flg << 8) << slave->cs)) |
(1 << slave->cs));
+ SSYNC();
debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
}
void spi_cs_deactivate(struct spi_slave *slave)
{
struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
- write_SPI_FLG(bss, read_SPI_FLG(bss) & ~(1 << slave->cs));
+ u16 flg;
+
+ /* make sure we force the cs to deassert rather than let the
+ * pin float back up. otherwise, exact timings may not be
+ * met some of the time leading to random behavior (ugh).
+ */
+ flg = read_SPI_FLG(bss) | ((!bss->flg << 8) << slave->cs);
+ write_SPI_FLG(bss, flg);
+ SSYNC();
+ debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
+
+ flg &= ~(1 << slave->cs);
+ write_SPI_FLG(bss, flg);
+ SSYNC();
debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
}
unsigned int max_hz, unsigned int mode)
{
struct bfin_spi_slave *bss;
+ ulong sclk;
u32 mmr_base;
u32 baud;
default: return NULL;
}
- baud = get_sclk() / (2 * max_hz);
+ sclk = get_sclk();
+ baud = sclk / (2 * max_hz);
+ /* baud should be rounded up */
+ if (sclk % (2 * max_hz))
+ baud += 1;
if (baud < 2)
baud = 2;
else if (baud > (u16)-1)
case 1: SET_MUX(f, 2, 1); f_fer |= PF7; break;
case 2: /* see G above */ g_fer |= PG15; break;
case 3: SET_MUX(h, 1, 3); f_fer |= PH4; break;
- case 4: /* no muxing */ break;
+ case 4: /* no muxing */ h_fer |= PH8; break;
case 5: SET_MUX(g, 1, 3); h_fer |= PG3; break;
case 6: /* no muxing */ break;
case 7: /* no muxing */ break;
SSYNC();
}
+#ifndef CONFIG_BFIN_SPI_IDLE_VAL
+# define CONFIG_BFIN_SPI_IDLE_VAL 0xff
+#endif
+
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
void *din, unsigned long flags)
{
/* todo: take advantage of hardware fifos and setup RX dma */
while (bytes--) {
- u8 value = (tx ? *tx++ : 0);
+ u8 value = (tx ? *tx++ : CONFIG_BFIN_SPI_IDLE_VAL);
debug("%s: tx:%x ", __func__, value);
write_SPI_TDBR(bss, value);
SSYNC();