power: pmic: Let PFUZE3000 see all 256 registers

[u-boot] / drivers / spi / cadence_qspi.h

diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
index c9a6142e82d865e60930338fdf00e2ea0da9f7ed..055900def001ffe2e6a1d76cfdbb5534b31fc5c3 100644 (file)
--- a/drivers/spi/cadence_qspi.h
+++ b/drivers/spi/cadence_qspi.h
@@ -1,8 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright (C) 2012
  * Altera Corporation <www.altera.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef __CADENCE_QSPI_H__
@@ -18,7 +17,12 @@ struct cadence_spi_platdata {
        unsigned int    max_hz;
        void            *regbase;
        void            *ahbbase;
+       bool            is_decoded_cs;
+       u32             fifo_depth;
+       u32             fifo_width;
+       u32             trigger_address;
 
+       /* Flash parameters */
        u32             page_size;
        u32             block_size;
        u32             tshsl_ns;
@@ -37,6 +41,7 @@ struct cadence_spi_priv {
        int             qspi_is_init;
        unsigned int    qspi_calibrated_hz;
        unsigned int    qspi_calibrated_cs;
+       unsigned int    previous_hz;
 };
 
 /* Functions call declaration */
@@ -51,7 +56,7 @@ int cadence_qspi_apb_command_write(void *reg_base_addr,
        unsigned int txlen,  const u8 *txbuf);
 
 int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
-       unsigned int cmdlen, const u8 *cmdbuf);
+       unsigned int cmdlen, unsigned int rx_width, const u8 *cmdbuf);
 int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
        unsigned int rxlen, u8 *rxbuf);
 int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
@@ -61,8 +66,7 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
 
 void cadence_qspi_apb_chipselect(void *reg_base,
        unsigned int chip_select, unsigned int decoder_enable);
-void cadence_qspi_apb_set_clk_mode(void *reg_base_addr,
-       unsigned int clk_pol, unsigned int clk_pha);
+void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode);
 void cadence_qspi_apb_config_baudrate_div(void *reg_base,
        unsigned int ref_clk_hz, unsigned int sclk_hz);
 void cadence_qspi_apb_delay(void *reg_base,