power: pmic: Let PFUZE3000 see all 256 registers

[u-boot] / drivers / spi / cadence_qspi_apb.c

diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 128c41d715e08a24b9be52be569c779ea82dc0ef..aa3a9ff5fa3bfcf6a399dedc522edfed4b582cff 100644 (file)
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -30,7 +30,7 @@
 #include <linux/errno.h>
 #include <wait_bit.h>
 #include <spi.h>
-#include <bouncebuf.h>
+#include <malloc.h>
 #include "cadence_qspi.h"
 
 #define CQSPI_REG_POLL_US                      1 /* 1us */
@@ -720,19 +720,22 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
 {
        unsigned int page_size = plat->page_size;
        unsigned int remaining = n_tx;
+       const u8 *bb_txbuf = txbuf;
+       void *bounce_buf = NULL;
        unsigned int write_bytes;
        int ret;
-       struct bounce_buffer bb;
-       u8 *bb_txbuf;
 
        /*
-        * Handle non-4-byte aligned accesses via bounce buffer to
-        * avoid data abort.
+        * Use bounce buffer for non 32 bit aligned txbuf to avoid data
+        * aborts
         */
-       ret = bounce_buffer_start(&bb, (void *)txbuf, n_tx, GEN_BB_READ);
-       if (ret)
-               return ret;
-       bb_txbuf = bb.bounce_buffer;
+       if ((uintptr_t)txbuf % 4) {
+               bounce_buf = malloc(n_tx);
+               if (!bounce_buf)
+                       return -ENOMEM;
+               memcpy(bounce_buf, txbuf, n_tx);
+               bb_txbuf = bounce_buf;
+       }
 
        /* Configure the indirect read transfer bytes */
        writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
@@ -768,18 +771,20 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
                printf("Indirect write completion error (%i)\n", ret);
                goto failwr;
        }
-       bounce_buffer_stop(&bb);
 
        /* Clear indirect completion status */
        writel(CQSPI_REG_INDIRECTWR_DONE,
               plat->regbase + CQSPI_REG_INDIRECTWR);
+       if (bounce_buf)
+               free(bounce_buf);
        return 0;
 
 failwr:
        /* Cancel the indirect write */
        writel(CQSPI_REG_INDIRECTWR_CANCEL,
               plat->regbase + CQSPI_REG_INDIRECTWR);
-       bounce_buffer_stop(&bb);
+       if (bounce_buf)
+               free(bounce_buf);
        return ret;
 }