#define CQSPI_FIFO_WIDTH (4)
-/* Controller sram size in word */
-#define CQSPI_REG_SRAM_SIZE_WORD (128)
-#define CQSPI_REG_SRAM_RESV_WORDS (2)
-#define CQSPI_REG_SRAM_PARTITION_WR (1)
-#define CQSPI_REG_SRAM_PARTITION_RD \
- (CQSPI_REG_SRAM_SIZE_WORD - CQSPI_REG_SRAM_RESV_WORDS)
#define CQSPI_REG_SRAM_THRESHOLD_WORDS (50)
/* Transfer mode */
unsigned int *dest_ptr = (unsigned int *)dest;
unsigned int *src_ptr = (unsigned int *)src_ahb_addr;
- while (remaining > 0) {
- if (remaining >= CQSPI_FIFO_WIDTH) {
- *dest_ptr = readl(src_ptr);
- remaining -= CQSPI_FIFO_WIDTH;
- } else {
- /* dangling bytes */
- temp = readl(src_ptr);
- memcpy(dest_ptr, &temp, remaining);
- break;
- }
+ while (remaining >= sizeof(dest_ptr)) {
+ *dest_ptr = readl(src_ptr);
+ remaining -= sizeof(src_ptr);
dest_ptr++;
}
+ if (remaining) {
+ /* dangling bytes */
+ temp = readl(src_ptr);
+ memcpy(dest_ptr, &temp, remaining);
+ }
return;
}
static void cadence_qspi_apb_write_fifo_data(const void *dest_ahb_addr,
const void *src, unsigned int bytes)
{
- unsigned int temp;
+ unsigned int temp = 0;
+ int i;
int remaining = bytes;
unsigned int *dest_ptr = (unsigned int *)dest_ahb_addr;
unsigned int *src_ptr = (unsigned int *)src;
- while (remaining > 0) {
- if (remaining >= CQSPI_FIFO_WIDTH) {
- writel(*src_ptr, dest_ptr);
- remaining -= sizeof(unsigned int);
- } else {
- /* dangling bytes */
- memcpy(&temp, src_ptr, remaining);
- writel(temp, dest_ptr);
- break;
- }
- src_ptr++;
+ while (remaining >= CQSPI_FIFO_WIDTH) {
+ for (i = CQSPI_FIFO_WIDTH/sizeof(src_ptr) - 1; i >= 0; i--)
+ writel(*(src_ptr+i), dest_ptr+i);
+ src_ptr += CQSPI_FIFO_WIDTH/sizeof(src_ptr);
+ remaining -= CQSPI_FIFO_WIDTH;
+ }
+ if (remaining) {
+ /* dangling bytes */
+ i = remaining/sizeof(dest_ptr);
+ memcpy(&temp, src_ptr+i, remaining % sizeof(dest_ptr));
+ writel(temp, dest_ptr+i);
+ for (--i; i >= 0; i--)
+ writel(*(src_ptr+i), dest_ptr+i);
}
-
return;
}
/* Configure the remap address register, no remap */
writel(0, plat->regbase + CQSPI_REG_REMAP);
+ /* Indirect mode configurations */
+ writel((plat->sram_size/2), plat->regbase + CQSPI_REG_SRAMPARTITION);
+
/* Disable all interrupts */
writel(0, plat->regbase + CQSPI_REG_IRQMASK);
writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
- /* Configure SRAM partition for read. */
- writel(CQSPI_REG_SRAM_PARTITION_RD, plat->regbase +
- CQSPI_REG_SRAMPARTITION);
-
/* Configure the opcode */
rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB;
writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
- writel(CQSPI_REG_SRAM_PARTITION_WR,
- plat->regbase + CQSPI_REG_SRAMPARTITION);
-
/* Configure the opcode */
reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB;
writel(reg, plat->regbase + CQSPI_REG_WR_INSTR);