DECLARE_GLOBAL_DATA_PTR;
/* fsl_dspi_platdata flags */
-#define DSPI_FLAG_REGMAP_ENDIAN_BIG (1 << 0)
+#define DSPI_FLAG_REGMAP_ENDIAN_BIG BIT(0)
/* idle data value */
#define DSPI_IDLE_VAL 0x0
priv = dev_get_priv(bus);
- /* processor special prepartion work */
+ /* processor special preparation work */
cpu_dspi_claim_bus(bus->seq, slave_plat->cs);
/* configure transfer mode */
plat->num_chipselect =
fdtdec_get_int(blob, node, "num-cs", FSL_DSPI_MAX_CHIPSELECT);
- addr = fdtdec_get_addr(blob, node, "reg");
+ addr = dev_get_addr(bus);
if (addr == FDT_ADDR_T_NONE) {
debug("DSPI: Can't get base address or size\n");
return -ENOMEM;
plat->speed_hz = fdtdec_get_int(blob,
node, "spi-max-frequency", FSL_DSPI_DEFAULT_SCK_FREQ);
- debug("DSPI: regs=0x%x, max-frequency=%d, endianess=%s, num-cs=%d\n",
- plat->regs_addr, plat->speed_hz,
+ debug("DSPI: regs=%pa, max-frequency=%d, endianess=%s, num-cs=%d\n",
+ &plat->regs_addr, plat->speed_hz,
plat->flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le",
plat->num_chipselect);