Prepare v2018.03-rc1

[u-boot] / drivers / spi / fsl_espi.c

diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c
index 375dc07f5f47f521d51544dd337a058873809a59..b1586d12912a60ade47d524feb1749774a98fccb 100644 (file)
--- a/drivers/spi/fsl_espi.c
+++ b/drivers/spi/fsl_espi.c
@@ -32,26 +32,26 @@ struct fsl_spi_slave {
 #define ESPI_MAX_CS_NUM                4
 #define ESPI_FIFO_WIDTH_BIT    32
 
-#define ESPI_EV_RNE            (1 << 9)
-#define ESPI_EV_TNF            (1 << 8)
-#define ESPI_EV_DON            (1 << 14)
-#define ESPI_EV_TXE            (1 << 15)
+#define ESPI_EV_RNE            BIT(9)
+#define ESPI_EV_TNF            BIT(8)
+#define ESPI_EV_DON            BIT(14)
+#define ESPI_EV_TXE            BIT(15)
 #define ESPI_EV_RFCNT_SHIFT    24
 #define ESPI_EV_RFCNT_MASK     (0x3f << ESPI_EV_RFCNT_SHIFT)
 
-#define ESPI_MODE_EN           (1 << 31)       /* Enable interface */
+#define ESPI_MODE_EN           BIT(31) /* Enable interface */
 #define ESPI_MODE_TXTHR(x)     ((x) << 8)      /* Tx FIFO threshold */
 #define ESPI_MODE_RXTHR(x)     ((x) << 0)      /* Rx FIFO threshold */
 
 #define ESPI_COM_CS(x)         ((x) << 30)
 #define ESPI_COM_TRANLEN(x)    ((x) << 0)
 
-#define ESPI_CSMODE_CI_INACTIVEHIGH    (1 << 31)
-#define ESPI_CSMODE_CP_BEGIN_EDGCLK    (1 << 30)
-#define ESPI_CSMODE_REV_MSB_FIRST      (1 << 29)
-#define ESPI_CSMODE_DIV16              (1 << 28)
+#define ESPI_CSMODE_CI_INACTIVEHIGH    BIT(31)
+#define ESPI_CSMODE_CP_BEGIN_EDGCLK    BIT(30)
+#define ESPI_CSMODE_REV_MSB_FIRST      BIT(29)
+#define ESPI_CSMODE_DIV16              BIT(28)
 #define ESPI_CSMODE_PM(x)              ((x) << 24)
-#define ESPI_CSMODE_POL_ASSERTED_LOW   (1 << 20)
+#define ESPI_CSMODE_POL_ASSERTED_LOW   BIT(20)
 #define ESPI_CSMODE_LEN(x)             ((x) << 16)
 #define ESPI_CSMODE_CSBEF(x)           ((x) << 12)
 #define ESPI_CSMODE_CSAFT(x)           ((x) << 8)