Merge branch 'master' of git://git.denx.de/u-boot-sunxi

[u-boot] / drivers / spi / fsl_qspi.c

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 0f3f7d97f0137fa7b258358119f8a0459d313a33..197f41f9db093b8123c6b04e47ea24c445426461 100644 (file)
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -1,9 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2013-2015 Freescale Semiconductor, Inc.
  *
  * Freescale Quad Serial Peripheral Interface (QSPI) driver
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -20,7 +19,8 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 #define RX_BUFFER_SIZE         0x80
-#ifdef CONFIG_MX6SX
+#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
+       defined(CONFIG_MX6ULL) || defined(CONFIG_MX7D)
 #define TX_BUFFER_SIZE         0x200
 #else
 #define TX_BUFFER_SIZE         0x40
@@ -155,6 +155,25 @@ static void qspi_write32(u32 flags, u32 *addr, u32 val)
                out_be32(addr, val) : out_le32(addr, val);
 }
 
+static inline int is_controller_busy(const struct fsl_qspi_priv *priv)
+{
+       u32 val;
+       const u32 mask = QSPI_SR_BUSY_MASK | QSPI_SR_AHB_ACC_MASK |
+                        QSPI_SR_IP_ACC_MASK;
+       unsigned int retry = 5;
+
+       do {
+               val = qspi_read32(priv->flags, &priv->regs->sr);
+
+               if ((~val & mask) == mask)
+                       return 0;
+
+               udelay(1);
+       } while (--retry);
+
+       return -ETIMEDOUT;
+}
+
 /* QSPI support swapping the flash read/write data
  * in hardware for LS102xA, but not for VF610 */
 static inline u32 qspi_endian_xchg(u32 data)
@@ -268,7 +287,8 @@ static void qspi_set_lut(struct fsl_qspi_priv *priv)
                             INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
                             PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 #endif
-#ifdef CONFIG_MX6SX
+#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
+       defined(CONFIG_MX6ULL) || defined(CONFIG_MX7D)
        /*
         * To MX6SX, OPRND0(TX_BUFFER_SIZE) can not work correctly.
         * So, Use IDATSZ in IPCR to determine the size and here set 0.
@@ -387,7 +407,7 @@ static inline void qspi_ahb_read(struct fsl_qspi_priv *priv, u8 *rxbuf, int len)
 {
        struct fsl_qspi_regs *regs = priv->regs;
        u32 mcr_reg;
-       void *rx_addr = NULL;
+       void *rx_addr;
 
        mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 
@@ -905,6 +925,11 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
        qspi->slave.max_write_size = TX_BUFFER_SIZE;
 
        mcr_val = qspi_read32(qspi->priv.flags, &regs->mcr);
+
+       /* Set endianness to LE for i.mx */
+       if (IS_ENABLED(CONFIG_MX6) || IS_ENABLED(CONFIG_MX7))
+               mcr_val = QSPI_MCR_END_CFD_LE;
+
        qspi_write32(qspi->priv.flags, &regs->mcr,
                     QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
                     (mcr_val & QSPI_MCR_END_CFD_MASK));
@@ -1011,11 +1036,7 @@ static int fsl_qspi_probe(struct udevice *bus)
        priv->num_chipselect = plat->num_chipselect;
 
        /* make sure controller is not busy anywhere */
-       ret = wait_for_bit(__func__, &priv->regs->sr,
-                          QSPI_SR_BUSY_MASK |
-                          QSPI_SR_AHB_ACC_MASK |
-                          QSPI_SR_IP_ACC_MASK,
-                          false, 100, false);
+       ret = is_controller_busy(priv);
 
        if (ret) {
                debug("ERROR : The controller is busy\n");
@@ -1023,6 +1044,11 @@ static int fsl_qspi_probe(struct udevice *bus)
        }
 
        mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);
+
+       /* Set endianness to LE for i.mx */
+       if (IS_ENABLED(CONFIG_MX6) || IS_ENABLED(CONFIG_MX7))
+               mcr_val = QSPI_MCR_END_CFD_LE;
+
        qspi_write32(priv->flags, &priv->regs->mcr,
                     QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
                     (mcr_val & QSPI_MCR_END_CFD_MASK));
@@ -1173,11 +1199,7 @@ static int fsl_qspi_claim_bus(struct udevice *dev)
        priv = dev_get_priv(bus);
 
        /* make sure controller is not busy anywhere */
-       ret = wait_for_bit(__func__, &priv->regs->sr,
-                          QSPI_SR_BUSY_MASK |
-                          QSPI_SR_AHB_ACC_MASK |
-                          QSPI_SR_IP_ACC_MASK,
-                          false, 100, false);
+       ret = is_controller_busy(priv);
 
        if (ret) {
                debug("ERROR : The controller is busy\n");
@@ -1227,6 +1249,8 @@ static const struct dm_spi_ops fsl_qspi_ops = {
 static const struct udevice_id fsl_qspi_ids[] = {
        { .compatible = "fsl,vf610-qspi" },
        { .compatible = "fsl,imx6sx-qspi" },
+       { .compatible = "fsl,imx6ul-qspi" },
+       { .compatible = "fsl,imx7d-qspi" },
        { }
 };