spi: cadence_spi: Sync DT bindings with Linux

[u-boot] / drivers / spi / fsl_qspi.c

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 1dfa89afc9c84eb6617359febef54687910ec064..eed52c15c8147677b10362d4e44411ce66700067 100644 (file)
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -14,6 +14,7 @@
 #include <dm.h>
 #include <errno.h>
 #include <watchdog.h>
+#include <wait_bit.h>
 #include "fsl_qspi.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -663,22 +664,20 @@ static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len)
        tx_size = (len > TX_BUFFER_SIZE) ?
                TX_BUFFER_SIZE : len;
 
-       size = tx_size / 4;
-       for (i = 0; i < size; i++) {
+       size = tx_size / 16;
+       /*
+        * There must be atleast 128bit data
+        * available in TX FIFO for any pop operation
+        */
+       if (tx_size % 16)
+               size++;
+       for (i = 0; i < size * 4; i++) {
                memcpy(&data, txbuf, 4);
                data = qspi_endian_xchg(data);
                qspi_write32(priv->flags, &regs->tbdr, data);
                txbuf += 4;
        }
 
-       size = tx_size % 4;
-       if (size) {
-               data = 0;
-               memcpy(&data, txbuf, size);
-               data = qspi_endian_xchg(data);
-               qspi_write32(priv->flags, &regs->tbdr, data);
-       }
-
        qspi_write32(priv->flags, &regs->ipcr,
                     (seqid << QSPI_IPCR_SEQID_SHIFT) | tx_size);
        while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
@@ -991,7 +990,7 @@ static int fsl_qspi_probe(struct udevice *bus)
        struct fsl_qspi_platdata *plat = dev_get_platdata(bus);
        struct fsl_qspi_priv *priv = dev_get_priv(bus);
        struct dm_spi_bus *dm_spi_bus;
-       int i;
+       int i, ret;
 
        dm_spi_bus = bus->uclass_priv;
 
@@ -1011,6 +1010,18 @@ static int fsl_qspi_probe(struct udevice *bus)
        priv->flash_num = plat->flash_num;
        priv->num_chipselect = plat->num_chipselect;
 
+       /* make sure controller is not busy anywhere */
+       ret = wait_for_bit_le32(&priv->regs->sr,
+                               QSPI_SR_BUSY_MASK |
+                               QSPI_SR_AHB_ACC_MASK |
+                               QSPI_SR_IP_ACC_MASK,
+                               false, 100, false);
+
+       if (ret) {
+               debug("ERROR : The controller is busy\n");
+               return ret;
+       }
+
        mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);
        qspi_write32(priv->flags, &priv->regs->mcr,
                     QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
@@ -1156,10 +1167,23 @@ static int fsl_qspi_claim_bus(struct udevice *dev)
        struct fsl_qspi_priv *priv;
        struct udevice *bus;
        struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+       int ret;
 
        bus = dev->parent;
        priv = dev_get_priv(bus);
 
+       /* make sure controller is not busy anywhere */
+       ret = wait_for_bit_le32(&priv->regs->sr,
+                               QSPI_SR_BUSY_MASK |
+                               QSPI_SR_AHB_ACC_MASK |
+                               QSPI_SR_IP_ACC_MASK,
+                               false, 100, false);
+
+       if (ret) {
+               debug("ERROR : The controller is busy\n");
+               return ret;
+       }
+
        priv->cur_amba_base = priv->amba_base[slave_plat->cs];
 
        qspi_module_disable(priv, 0);