+// SPDX-License-Identifier: GPL-2.0+
/*
* spi driver for rockchip
*
*
* (C) Copyright 2008-2013 Rockchip Electronics
* Peter, Software Engineering, <superpeter.cai@gmail.com>.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm/pinctrl.h>
#include "rk_spi.h"
-DECLARE_GLOBAL_DATA_PTR;
-
/* Change to 1 to output registers at the start of each transaction */
#define DEBUG_RK_SPI 0
*/
if (clk_div > 0xfffe) {
clk_div = 0xfffe;
- debug("%s: can't divide down to %d hz (actual will be %d hz)\n",
+ debug("%s: can't divide down to %d Hz (actual will be %d Hz)\n",
__func__, speed, priv->input_rate / clk_div);
}
struct rockchip_spi_priv *priv = dev_get_priv(bus);
int ret;
- plat->base = devfdt_get_addr(bus);
+ plat->base = dev_read_addr(bus);
ret = clk_get_by_index(bus, 0, &priv->clk);
if (ret < 0) {
static int rockchip_spi_calc_modclk(ulong max_freq)
{
+ /*
+ * While this is not strictly correct for the RK3368, as the
+ * GPLL will be 576MHz, things will still work, as the
+ * clk_set_rate(...) implementation in our clock-driver will
+ * chose the next closest rate not exceeding what we request
+ * based on the output of this function.
+ */
+
unsigned div;
const unsigned long gpll_hz = 594000000UL;
static const struct udevice_id rockchip_spi_ids[] = {
{ .compatible = "rockchip,rk3288-spi" },
+ { .compatible = "rockchip,rk3368-spi" },
{ .compatible = "rockchip,rk3399-spi" },
{ }
};