#include <common.h>
#include <clk.h>
#include <dm.h>
+#include <dt-structs.h>
#include <errno.h>
#include <spi.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/periph.h>
#include <dm/pinctrl.h>
#include "rk_spi.h"
-DECLARE_GLOBAL_DATA_PTR;
-
/* Change to 1 to output registers at the start of each transaction */
#define DEBUG_RK_SPI 0
struct rockchip_spi_platdata {
- enum periph_id periph_id;
- struct udevice *pinctrl;
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct dtd_rockchip_rk3288_spi of_plat;
+#endif
s32 frequency; /* Default clock frequency, -1 for none */
fdt_addr_t base;
uint deactivate_delay_us; /* Delay to wait after deactivate */
+ uint activate_delay_us; /* Delay to wait after activate */
};
struct rockchip_spi_priv {
struct rockchip_spi *regs;
- struct udevice *clk_gpll;
+ struct clk clk;
unsigned int max_freq;
unsigned int mode;
- enum periph_id periph_id; /* Peripheral ID for this device */
ulong last_transaction_us; /* Time of last transaction end */
u8 bits_per_word; /* max 16 bits per word */
u8 n_bytes;
unsigned int speed_hz;
+ unsigned int last_speed_hz;
unsigned int tmode;
uint input_rate;
};
static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed)
{
- uint clk_div;
+ /*
+ * We should try not to exceed the speed requested by the caller:
+ * when selecting a divider, we need to make sure we round up.
+ */
+ uint clk_div = DIV_ROUND_UP(priv->input_rate, speed);
+
+ /* The baudrate register (BAUDR) is defined as a 32bit register where
+ * the upper 16bit are reserved and having 'Fsclk_out' in the lower
+ * 16bits with 'Fsclk_out' defined as follows:
+ *
+ * Fsclk_out = Fspi_clk/ SCKDV
+ * Where SCKDV is any even value between 2 and 65534.
+ */
+ if (clk_div > 0xfffe) {
+ clk_div = 0xfffe;
+ debug("%s: can't divide down to %d Hz (actual will be %d Hz)\n",
+ __func__, speed, priv->input_rate / clk_div);
+ }
+
+ /* Round up to the next even 16bit number */
+ clk_div = (clk_div + 1) & 0xfffe;
- clk_div = clk_get_divisor(priv->input_rate, speed);
debug("spi speed %u, div %u\n", speed, clk_div);
- writel(clk_div, &priv->regs->baudr);
+ clrsetbits_le32(&priv->regs->baudr, 0xffff, clk_div);
+ priv->last_speed_hz = speed;
}
static int rkspi_wait_till_not_busy(struct rockchip_spi *regs)
return 0;
}
-static void spi_cs_activate(struct rockchip_spi *regs, uint cs)
+static void spi_cs_activate(struct udevice *dev, uint cs)
{
+ struct udevice *bus = dev->parent;
+ struct rockchip_spi_platdata *plat = bus->platdata;
+ struct rockchip_spi_priv *priv = dev_get_priv(bus);
+ struct rockchip_spi *regs = priv->regs;
+
+ /* If it's too soon to do another transaction, wait */
+ if (plat->deactivate_delay_us && priv->last_transaction_us) {
+ ulong delay_us; /* The delay completed so far */
+ delay_us = timer_get_us() - priv->last_transaction_us;
+ if (delay_us < plat->deactivate_delay_us)
+ udelay(plat->deactivate_delay_us - delay_us);
+ }
+
debug("activate cs%u\n", cs);
writel(1 << cs, ®s->ser);
+ if (plat->activate_delay_us)
+ udelay(plat->activate_delay_us);
}
-static void spi_cs_deactivate(struct rockchip_spi *regs, uint cs)
+static void spi_cs_deactivate(struct udevice *dev, uint cs)
{
+ struct udevice *bus = dev->parent;
+ struct rockchip_spi_platdata *plat = bus->platdata;
+ struct rockchip_spi_priv *priv = dev_get_priv(bus);
+ struct rockchip_spi *regs = priv->regs;
+
debug("deactivate cs%u\n", cs);
writel(0, ®s->ser);
+
+ /* Remember time of this transaction so we can honour the bus delay */
+ if (plat->deactivate_delay_us)
+ priv->last_transaction_us = timer_get_us();
}
-static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+static int conv_of_platdata(struct udevice *dev)
{
- struct rockchip_spi_platdata *plat = bus->platdata;
- const void *blob = gd->fdt_blob;
- int node = bus->of_offset;
+ struct rockchip_spi_platdata *plat = dev->platdata;
+ struct dtd_rockchip_rk3288_spi *dtplat = &plat->of_plat;
+ struct rockchip_spi_priv *priv = dev_get_priv(dev);
int ret;
- plat->base = dev_get_addr(bus);
- ret = uclass_get_device(UCLASS_PINCTRL, 0, &plat->pinctrl);
- if (ret)
+ plat->base = dtplat->reg[0];
+ plat->frequency = 20000000;
+ ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);
+ if (ret < 0)
return ret;
- ret = pinctrl_get_periph_id(plat->pinctrl, bus);
+ dev->req_seq = 0;
+
+ return 0;
+}
+#endif
+
+static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
+{
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
+ struct rockchip_spi_priv *priv = dev_get_priv(bus);
+ int ret;
+
+ plat->base = dev_read_addr(bus);
+ ret = clk_get_by_index(bus, 0, &priv->clk);
if (ret < 0) {
- debug("%s: Could not get peripheral ID for %s: %d\n", __func__,
+ debug("%s: Could not get clock for %s: %d\n", __func__,
bus->name, ret);
- return -FDT_ERR_NOTFOUND;
+ return ret;
}
- plat->periph_id = ret;
-
- plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
- 50000000);
- plat->deactivate_delay_us = fdtdec_get_int(blob, node,
- "spi-deactivate-delay", 0);
- debug("%s: base=%x, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
- __func__, plat->base, plat->periph_id, plat->frequency,
+
+ plat->frequency =
+ dev_read_u32_default(bus, "spi-max-frequency", 50000000);
+ plat->deactivate_delay_us =
+ dev_read_u32_default(bus, "spi-deactivate-delay", 0);
+ plat->activate_delay_us =
+ dev_read_u32_default(bus, "spi-activate-delay", 0);
+
+ debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n",
+ __func__, (uint)plat->base, plat->frequency,
plat->deactivate_delay_us);
+#endif
return 0;
}
+static int rockchip_spi_calc_modclk(ulong max_freq)
+{
+ /*
+ * While this is not strictly correct for the RK3368, as the
+ * GPLL will be 576MHz, things will still work, as the
+ * clk_set_rate(...) implementation in our clock-driver will
+ * chose the next closest rate not exceeding what we request
+ * based on the output of this function.
+ */
+
+ unsigned div;
+ const unsigned long gpll_hz = 594000000UL;
+
+ /*
+ * We need to find an input clock that provides at least twice
+ * the maximum frequency and can be generated from the assumed
+ * speed of GPLL (594MHz) using an integer divider.
+ *
+ * To give us more achievable bitrates at higher speeds (these
+ * are generated by dividing by an even 16-bit integer from
+ * this frequency), we try to have an input frequency of at
+ * least 4x our max_freq.
+ */
+
+ div = DIV_ROUND_UP(gpll_hz, max_freq * 4);
+ return gpll_hz / div;
+}
+
static int rockchip_spi_probe(struct udevice *bus)
{
struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
int ret;
debug("%s: probe\n", __func__);
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ ret = conv_of_platdata(bus);
+ if (ret)
+ return ret;
+#endif
priv->regs = (struct rockchip_spi *)plat->base;
priv->last_transaction_us = timer_get_us();
priv->max_freq = plat->frequency;
- priv->periph_id = plat->periph_id;
- ret = uclass_get_device(UCLASS_CLK, CLK_GENERAL, &priv->clk_gpll);
- if (ret) {
- debug("%s: Failed to find CLK_GENERAL: %d\n", __func__, ret);
- return ret;
- }
- /*
- * Use 99 MHz as our clock since it divides nicely into 594 MHz which
- * is the assumed speed for CLK_GENERAL.
- */
- ret = clk_set_periph_rate(priv->clk_gpll, plat->periph_id, 99000000);
+ /* Clamp the value from the DTS against any hardware limits */
+ if (priv->max_freq > ROCKCHIP_SPI_MAX_RATE)
+ priv->max_freq = ROCKCHIP_SPI_MAX_RATE;
+
+ /* Find a module-input clock that fits with the max_freq setting */
+ ret = clk_set_rate(&priv->clk,
+ rockchip_spi_calc_modclk(priv->max_freq));
if (ret < 0) {
debug("%s: Failed to set clock: %d\n", __func__, ret);
return ret;
static int rockchip_spi_claim_bus(struct udevice *dev)
{
struct udevice *bus = dev->parent;
- struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
struct rockchip_spi_priv *priv = dev_get_priv(bus);
struct rockchip_spi *regs = priv->regs;
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
u8 spi_dfs, spi_tf;
uint ctrlr0;
- int ret;
/* Disable the SPI hardware */
rkspi_enable_chip(regs, 0);
return -EPROTONOSUPPORT;
}
- rkspi_set_clk(priv, priv->speed_hz);
+ if (priv->speed_hz != priv->last_speed_hz)
+ rkspi_set_clk(priv, priv->speed_hz);
/* Operation Mode */
ctrlr0 = OMOD_MASTER << OMOD_SHIFT;
/* Data Frame Size */
- ctrlr0 |= spi_dfs & DFS_MASK << DFS_SHIFT;
+ ctrlr0 |= spi_dfs << DFS_SHIFT;
/* set SPI mode 0..3 */
if (priv->mode & SPI_CPOL)
ctrlr0 |= FBM_MSB << FBM_SHIFT;
/* Byte and Halfword Transform */
- ctrlr0 |= (spi_tf & HALF_WORD_MASK) << HALF_WORD_TX_SHIFT;
+ ctrlr0 |= spi_tf << HALF_WORD_TX_SHIFT;
/* Rxd Sample Delay */
ctrlr0 |= 0 << RXDSD_SHIFT;
writel(ctrlr0, ®s->ctrlr0);
- ret = pinctrl_request(plat->pinctrl, priv->periph_id, slave_plat->cs);
- if (ret) {
- debug("%s: Cannot request pinctrl: %d\n", __func__, ret);
- return ret;
- }
-
return 0;
}
static int rockchip_spi_release_bus(struct udevice *dev)
{
+ struct udevice *bus = dev->parent;
+ struct rockchip_spi_priv *priv = dev_get_priv(bus);
+
+ rkspi_enable_chip(priv->regs, false);
+
return 0;
}
/* Assert CS before transfer */
if (flags & SPI_XFER_BEGIN)
- spi_cs_activate(regs, slave_plat->cs);
+ spi_cs_activate(dev, slave_plat->cs);
while (len > 0) {
int todo = min(len, 0xffff);
- rkspi_enable_chip(regs, true);
+ rkspi_enable_chip(regs, false);
writel(todo - 1, ®s->ctrlr1);
rkspi_enable_chip(regs, true);
/* Deassert CS after transfer */
if (flags & SPI_XFER_END)
- spi_cs_deactivate(regs, slave_plat->cs);
+ spi_cs_deactivate(dev, slave_plat->cs);
rkspi_enable_chip(regs, false);
{
struct rockchip_spi_priv *priv = dev_get_priv(bus);
- if (speed > ROCKCHIP_SPI_MAX_RATE)
- return -EINVAL;
+ /* Clamp to the maximum frequency specified in the DTS */
if (speed > priv->max_freq)
speed = priv->max_freq;
+
priv->speed_hz = speed;
return 0;
static const struct udevice_id rockchip_spi_ids[] = {
{ .compatible = "rockchip,rk3288-spi" },
+ { .compatible = "rockchip,rk3368-spi" },
+ { .compatible = "rockchip,rk3399-spi" },
{ }
};
U_BOOT_DRIVER(rockchip_spi) = {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ .name = "rockchip_rk3288_spi",
+#else
.name = "rockchip_spi",
+#endif
.id = UCLASS_SPI,
.of_match = rockchip_spi_ids,
.ops = &rockchip_spi_ops,
projects / u-boot / blobdiff