ARM: socfpga: Clean up Kconfig entries

[u-boot] / drivers / spi / stm32_qspi.c

diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c
index 123a1f368d8a2e9b2c8c308961186140639282f5..7d1801280773937c6e31f713755560bc10436017 100644 (file)
--- a/drivers/spi/stm32_qspi.c
+++ b/drivers/spi/stm32_qspi.c
@@ -1,11 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2016
  *
  * Michael Kurz, <michi.kurz@gmail.com>
  *
  * STM32 QSPI driver
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -16,7 +15,7 @@
 #include <dm.h>
 #include <errno.h>
 #include <asm/arch/stm32.h>
-#include <asm/arch/stm32_defs.h>
+#include <clk.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -164,6 +163,7 @@ struct stm32_qspi_platdata {
 
 struct stm32_qspi_priv {
        struct stm32_qspi_regs *regs;
+       ulong clock_rate;
        u32 max_hz;
        u32 mode;
 
@@ -411,7 +411,7 @@ static int stm32_qspi_ofdata_to_platdata(struct udevice *bus)
        struct fdt_resource res_regs, res_mem;
        struct stm32_qspi_platdata *plat = bus->platdata;
        const void *blob = gd->fdt_blob;
-       int node = bus->of_offset;
+       int node = dev_of_offset(bus);
        int ret;
 
        ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
@@ -457,7 +457,27 @@ static int stm32_qspi_probe(struct udevice *bus)
 
        priv->max_hz = plat->max_hz;
 
-       clock_setup(QSPI_CLOCK_CFG);
+#ifdef CONFIG_CLK
+       int ret;
+       struct clk clk;
+       ret = clk_get_by_index(bus, 0, &clk);
+       if (ret < 0)
+               return ret;
+
+       ret = clk_enable(&clk);
+
+       if (ret) {
+               dev_err(bus, "failed to enable clock\n");
+               return ret;
+       }
+
+       priv->clock_rate = clk_get_rate(&clk);
+       if (priv->clock_rate < 0) {
+               clk_disable(&clk);
+               return priv->clock_rate;
+       }
+
+#endif
 
        setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT);
 
@@ -522,7 +542,7 @@ static int stm32_qspi_set_speed(struct udevice *bus, uint speed)
        if (speed > plat->max_hz)
                speed = plat->max_hz;
 
-       u32 qspi_clk = clock_get(CLOCK_AHB);
+       u32 qspi_clk = priv->clock_rate;
        u32 prescaler = 255;
        if (speed > 0) {
                prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1;