spi: stm32_qspi: Add st, stm32f469-qspi compatible string

[u-boot] / drivers / spi / stm32_qspi.c

diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c
index 05358ebf4cd1bbb7512acf7d4049b53e60dd6191..9fe8b297a4580129bae44faabd1ba660ec6ecc1b 100644 (file)
--- a/drivers/spi/stm32_qspi.c
+++ b/drivers/spi/stm32_qspi.c
@@ -1,22 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2016
  *
  * Michael Kurz, <michi.kurz@gmail.com>
  *
  * STM32 QSPI driver
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <errno.h>
 #include <malloc.h>
 #include <spi.h>
 #include <spi_flash.h>
 #include <asm/io.h>
-#include <dm.h>
-#include <errno.h>
 #include <asm/arch/stm32.h>
-#include <asm/arch/stm32_defs.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -164,6 +163,7 @@ struct stm32_qspi_platdata {
 
 struct stm32_qspi_priv {
        struct stm32_qspi_regs *regs;
+       ulong clock_rate;
        u32 max_hz;
        u32 mode;
 
@@ -206,6 +206,7 @@ static void _stm32_qspi_wait_for_ftf(struct stm32_qspi_priv *priv)
 static void _stm32_qspi_set_flash_size(struct stm32_qspi_priv *priv, u32 size)
 {
        u32 fsize = fls(size) - 1;
+
        clrsetbits_le32(&priv->regs->dcr,
                        STM32_QSPI_DCR_FSIZE_MASK << STM32_QSPI_DCR_FSIZE_SHIFT,
                        fsize << STM32_QSPI_DCR_FSIZE_SHIFT);
@@ -255,13 +256,15 @@ static unsigned int _stm32_qspi_gen_ccr(struct stm32_qspi_priv *priv)
 }
 
 static void _stm32_qspi_enable_mmap(struct stm32_qspi_priv *priv,
-               struct spi_flash *flash)
+                                   struct spi_flash *flash)
 {
+       unsigned int ccr_reg;
+
        priv->command = flash->read_cmd | CMD_HAS_ADR | CMD_HAS_DATA
                        | CMD_HAS_DUMMY;
        priv->dummycycles = flash->dummy_byte * 8;
 
-       unsigned int ccr_reg = _stm32_qspi_gen_ccr(priv);
+       ccr_reg = _stm32_qspi_gen_ccr(priv);
        ccr_reg |= (STM32_QSPI_CCR_MEM_MAP << STM32_QSPI_CCR_FMODE_SHIFT);
 
        _stm32_qspi_wait_for_not_busy(priv);
@@ -291,10 +294,12 @@ static void _stm32_qspi_start_xfer(struct stm32_qspi_priv *priv, u32 cr_reg)
 }
 
 static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv,
-               struct spi_flash *flash, unsigned int bitlen,
-               const u8 *dout, u8 *din, unsigned long flags)
+                           struct spi_flash *flash, unsigned int bitlen,
+                           const u8 *dout, u8 *din, unsigned long flags)
 {
        unsigned int words = bitlen / 8;
+       u32 ccr_reg;
+       int i;
 
        if (flags & SPI_XFER_MMAP) {
                _stm32_qspi_enable_mmap(priv, flash);
@@ -346,7 +351,7 @@ static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv,
                }
 
                if (flags & SPI_XFER_END) {
-                       u32 ccr_reg = _stm32_qspi_gen_ccr(priv);
+                       ccr_reg = _stm32_qspi_gen_ccr(priv);
                        ccr_reg |= STM32_QSPI_CCR_IND_WRITE
                                        << STM32_QSPI_CCR_FMODE_SHIFT;
 
@@ -365,7 +370,7 @@ static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv,
 
                                debug("%s: words:%d data:", __func__, words);
 
-                               int i = 0;
+                               i = 0;
                                while (words > i) {
                                        writeb(dout[i], &priv->regs->dr);
                                        debug("%02x ", dout[i]);
@@ -379,7 +384,7 @@ static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv,
                        }
                }
        } else if (din) {
-               u32 ccr_reg = _stm32_qspi_gen_ccr(priv);
+               ccr_reg = _stm32_qspi_gen_ccr(priv);
                ccr_reg |= STM32_QSPI_CCR_IND_READ
                                << STM32_QSPI_CCR_FMODE_SHIFT;
 
@@ -394,7 +399,7 @@ static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv,
 
                debug("%s: data:", __func__);
 
-               int i = 0;
+               i = 0;
                while (words > i) {
                        din[i] = readb(&priv->regs->dr);
                        debug("%02x ", din[i]);
@@ -415,13 +420,13 @@ static int stm32_qspi_ofdata_to_platdata(struct udevice *bus)
        int ret;
 
        ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
-                                    "QuadSPI", &res_regs);
+                                    "qspi", &res_regs);
        if (ret) {
                debug("Error: can't get regs base addresses(ret = %d)!\n", ret);
                return -ENOMEM;
        }
        ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
-                                    "QuadSPI-memory", &res_mem);
+                                    "qspi_mm", &res_mem);
        if (ret) {
                debug("Error: can't get mmap base address(ret = %d)!\n", ret);
                return -ENOMEM;
@@ -448,6 +453,8 @@ static int stm32_qspi_probe(struct udevice *bus)
        struct stm32_qspi_platdata *plat = dev_get_platdata(bus);
        struct stm32_qspi_priv *priv = dev_get_priv(bus);
        struct dm_spi_bus *dm_spi_bus;
+       struct clk clk;
+       int ret;
 
        dm_spi_bus = bus->uclass_priv;
 
@@ -457,7 +464,23 @@ static int stm32_qspi_probe(struct udevice *bus)
 
        priv->max_hz = plat->max_hz;
 
-       clock_setup(QSPI_CLOCK_CFG);
+       ret = clk_get_by_index(bus, 0, &clk);
+       if (ret < 0)
+               return ret;
+
+       ret = clk_enable(&clk);
+
+       if (ret) {
+               dev_err(bus, "failed to enable clock\n");
+               return ret;
+       }
+
+       priv->clock_rate = clk_get_rate(&clk);
+       if (priv->clock_rate < 0) {
+               clk_disable(&clk);
+               return priv->clock_rate;
+       }
+
 
        setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT);
 
@@ -500,7 +523,7 @@ static int stm32_qspi_release_bus(struct udevice *dev)
 }
 
 static int stm32_qspi_xfer(struct udevice *dev, unsigned int bitlen,
-               const void *dout, void *din, unsigned long flags)
+                          const void *dout, void *din, unsigned long flags)
 {
        struct stm32_qspi_priv *priv;
        struct udevice *bus;
@@ -518,12 +541,13 @@ static int stm32_qspi_set_speed(struct udevice *bus, uint speed)
 {
        struct stm32_qspi_platdata *plat = bus->platdata;
        struct stm32_qspi_priv *priv = dev_get_priv(bus);
+       u32 qspi_clk = priv->clock_rate;
+       u32 prescaler = 255;
+       u32 csht;
 
        if (speed > plat->max_hz)
                speed = plat->max_hz;
 
-       u32 qspi_clk = clock_get(CLOCK_AHB);
-       u32 prescaler = 255;
        if (speed > 0) {
                prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1;
                if (prescaler > 255)
@@ -532,7 +556,7 @@ static int stm32_qspi_set_speed(struct udevice *bus, uint speed)
                        prescaler = 0;
        }
 
-       u32 csht = DIV_ROUND_UP((5 * qspi_clk) / (prescaler + 1), 100000000);
+       csht = DIV_ROUND_UP((5 * qspi_clk) / (prescaler + 1), 100000000);
        csht = (csht - 1) & STM32_QSPI_DCR_CSHT_MASK;
 
        _stm32_qspi_wait_for_not_busy(priv);
@@ -542,7 +566,6 @@ static int stm32_qspi_set_speed(struct udevice *bus, uint speed)
                        STM32_QSPI_CR_PRESCALER_SHIFT,
                        prescaler << STM32_QSPI_CR_PRESCALER_SHIFT);
 
-
        clrsetbits_le32(&priv->regs->dcr,
                        STM32_QSPI_DCR_CSHT_MASK << STM32_QSPI_DCR_CSHT_SHIFT,
                        csht << STM32_QSPI_DCR_CSHT_SHIFT);
@@ -612,6 +635,7 @@ static const struct dm_spi_ops stm32_qspi_ops = {
 
 static const struct udevice_id stm32_qspi_ids[] = {
        { .compatible = "st,stm32-qspi" },
+       { .compatible = "st,stm32f469-qspi" },
        { }
 };