dm: core: Add a function to decode a memory region

[u-boot] / drivers / spi / tegra20_slink.c

diff --git a/drivers/spi/tegra20_slink.c b/drivers/spi/tegra20_slink.c
index 238edec23ba59e65d9b90e0b8a0f485b5b9c66ce..d55e833cc24eca636ad614a464b7704b80cea557 100644 (file)
--- a/drivers/spi/tegra20_slink.c
+++ b/drivers/spi/tegra20_slink.c
@@ -1,9 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * NVIDIA Tegra SPI-SLINK controller
  *
  * Copyright (c) 2010-2013 NVIDIA Corporation
- *
- * SPDX-License-Identifier:    GPL-2.0
  */
 
 #include <common.h>
@@ -94,10 +93,10 @@ static int tegra30_spi_ofdata_to_platdata(struct udevice *bus)
 {
        struct tegra_spi_platdata *plat = bus->platdata;
        const void *blob = gd->fdt_blob;
-       int node = bus->of_offset;
+       int node = dev_of_offset(bus);
 
-       plat->base = dev_get_addr(bus);
-       plat->periph_id = clock_decode_periph_id(blob, node);
+       plat->base = devfdt_get_addr(bus);
+       plat->periph_id = clock_decode_periph_id(bus);
 
        if (plat->periph_id == PERIPH_ID_NONE) {
                debug("%s: could not decode periph id %d\n", __func__,
@@ -128,6 +127,10 @@ static int tegra30_spi_probe(struct udevice *bus)
        priv->freq = plat->frequency;
        priv->periph_id = plat->periph_id;
 
+       /* Change SPI clock to correct frequency, PLLP_OUT0 source */
+       clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
+                              priv->freq);
+
        return 0;
 }