spi: cadence_qspi: Move DT prop code to match layout

[u-boot] / drivers / spi / ti_qspi.c

diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index 1e2c432ede66b04b13a4991acd8de16531cedd50..6f9f983524d1f051158f5508b32cbeb75fb109dc 100644 (file)
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -16,6 +16,7 @@
 #include <asm/omap_gpio.h>
 #include <asm/omap_common.h>
 #include <asm/ti-common/ti-edma3.h>
+#include <linux/kernel.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -118,21 +119,18 @@ static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
        if (!hz)
                clk_div = 0;
        else
-               clk_div = (priv->fclk / hz) - 1;
+               clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1;
+
+       /* truncate clk_div value to QSPI_CLK_DIV_MAX */
+       if (clk_div > QSPI_CLK_DIV_MAX)
+               clk_div = QSPI_CLK_DIV_MAX;
 
        debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
 
        /* disable SCLK */
        writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
               &priv->base->clk_ctrl);
-
-       /* assign clk_div values */
-       if (clk_div < 0)
-               clk_div = 0;
-       else if (clk_div > QSPI_CLK_DIV_MAX)
-               clk_div = QSPI_CLK_DIV_MAX;
-
-       /* enable SCLK */
+       /* enable SCLK and program the clk divider */
        writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
 }
 
@@ -226,13 +224,6 @@ static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen,
                priv->cmd |= QSPI_3_PIN;
        priv->cmd |= 0xfff;
 
-/* FIXME: This delay is required for successfull
- * completion of read/write/erase. Once its root
- * caused, it will be remove from the driver.
- */
-#ifdef CONFIG_AM43XX
-       udelay(100);
-#endif
        while (words) {
                u8 xfer_len = 0;
 
@@ -363,7 +354,7 @@ static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv)
                        QSPI_SETUP0_NUM_D_BYTES_8_BITS |
                        QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE |
                        QSPI_NUM_DUMMY_BITS);
-       slave->mode_rx = SPI_RX_QUAD;
+       slave->mode |= SPI_RX_QUAD;
 #else
        memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
                        QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
@@ -392,7 +383,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 
        priv->base = (struct ti_qspi_regs *)QSPI_BASE;
        priv->mode = mode;
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+#if defined(CONFIG_DRA7XX)
        priv->ctrl_mod_mmap = (void *)CORE_CTRL_IO;
        priv->slave.memory_map = (void *)MMAP_START_ADDR_DRA;
        priv->fclk = QSPI_DRA7XX_FCLK;
@@ -449,7 +440,7 @@ static void __ti_qspi_setup_memorymap(struct ti_qspi_priv *priv,
                                      bool enable)
 {
        u32 memval;
-       u32 mode = slave->mode_rx & (SPI_RX_QUAD | SPI_RX_DUAL);
+       u32 mode = slave->mode & (SPI_RX_QUAD | SPI_RX_DUAL);
 
        if (!enable) {
                writel(0, &priv->base->setup0);
@@ -463,7 +454,7 @@ static void __ti_qspi_setup_memorymap(struct ti_qspi_priv *priv,
                memval |= QSPI_CMD_READ_QUAD;
                memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
                memval |= QSPI_SETUP0_READ_QUAD;
-               slave->mode_rx = SPI_RX_QUAD;
+               slave->mode |= SPI_RX_QUAD;
                break;
        case SPI_RX_DUAL:
                memval |= QSPI_CMD_READ_DUAL;