spi: cadence_qspi: Move DT prop code to match layout

[u-boot] / drivers / spi / ti_qspi.c

diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index 52520dff6325ff3e298502c0bb09a0eb2f9a3171..6f9f983524d1f051158f5508b32cbeb75fb109dc 100644 (file)
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -16,6 +16,7 @@
 #include <asm/omap_gpio.h>
 #include <asm/omap_common.h>
 #include <asm/ti-common/ti-edma3.h>
+#include <linux/kernel.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -118,21 +119,18 @@ static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
        if (!hz)
                clk_div = 0;
        else
-               clk_div = (priv->fclk / hz) - 1;
+               clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1;
+
+       /* truncate clk_div value to QSPI_CLK_DIV_MAX */
+       if (clk_div > QSPI_CLK_DIV_MAX)
+               clk_div = QSPI_CLK_DIV_MAX;
 
        debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
 
        /* disable SCLK */
        writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
               &priv->base->clk_ctrl);
-
-       /* assign clk_div values */
-       if (clk_div < 0)
-               clk_div = 0;
-       else if (clk_div > QSPI_CLK_DIV_MAX)
-               clk_div = QSPI_CLK_DIV_MAX;
-
-       /* enable SCLK */
+       /* enable SCLK and program the clk divider */
        writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
 }
 
@@ -385,7 +383,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 
        priv->base = (struct ti_qspi_regs *)QSPI_BASE;
        priv->mode = mode;
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+#if defined(CONFIG_DRA7XX)
        priv->ctrl_mod_mmap = (void *)CORE_CTRL_IO;
        priv->slave.memory_map = (void *)MMAP_START_ADDR_DRA;
        priv->fclk = QSPI_DRA7XX_FCLK;