DW SPI: Get clock value from Device Tree

[u-boot] / drivers / spi / zynq_qspi.c

diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c
index 8aa61d7a507f93fc8892968e20a609993d08c4f6..255e02f585da4a9a6df77d6d477b3464eafeb097 100644 (file)
--- a/drivers/spi/zynq_qspi.c
+++ b/drivers/spi/zynq_qspi.c
@@ -16,20 +16,21 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* zynq qspi register bit masks ZYNQ_QSPI_<REG>_<BIT>_MASK */
-#define ZYNQ_QSPI_CR_IFMODE_MASK       (1 << 31)       /* Flash intrface mode*/
-#define ZYNQ_QSPI_CR_MSA_MASK          (1 << 15)       /* Manual start enb */
-#define ZYNQ_QSPI_CR_MCS_MASK          (1 << 14)       /* Manual chip select */
-#define ZYNQ_QSPI_CR_PCS_MASK          (1 << 10)       /* Peri chip select */
-#define ZYNQ_QSPI_CR_FW_MASK           (0x3 << 6)      /* FIFO width */
-#define ZYNQ_QSPI_CR_SS_MASK           (0xF << 10)     /* Slave Select */
-#define ZYNQ_QSPI_CR_BAUD_MASK         (0x7 << 3)      /* Baud rate div */
-#define ZYNQ_QSPI_CR_CPHA_MASK         (1 << 2)        /* Clock phase */
-#define ZYNQ_QSPI_CR_CPOL_MASK         (1 << 1)        /* Clock polarity */
-#define ZYNQ_QSPI_CR_MSTREN_MASK       (1 << 0)        /* Mode select */
-#define ZYNQ_QSPI_IXR_RXNEMPTY_MASK    (1 << 4)        /* RX_FIFO_not_empty */
-#define ZYNQ_QSPI_IXR_TXOW_MASK                (1 << 2)        /* TX_FIFO_not_full */
-#define ZYNQ_QSPI_IXR_ALL_MASK         0x7F            /* All IXR bits */
-#define ZYNQ_QSPI_ENR_SPI_EN_MASK      (1 << 0)        /* SPI Enable */
+#define ZYNQ_QSPI_CR_IFMODE_MASK       BIT(31) /* Flash intrface mode*/
+#define ZYNQ_QSPI_CR_MSA_MASK          BIT(15) /* Manual start enb */
+#define ZYNQ_QSPI_CR_MCS_MASK          BIT(14) /* Manual chip select */
+#define ZYNQ_QSPI_CR_PCS_MASK          BIT(10) /* Peri chip select */
+#define ZYNQ_QSPI_CR_FW_MASK           GENMASK(7, 6)   /* FIFO width */
+#define ZYNQ_QSPI_CR_SS_MASK           GENMASK(13, 10) /* Slave Select */
+#define ZYNQ_QSPI_CR_BAUD_MASK         GENMASK(5, 3)   /* Baud rate div */
+#define ZYNQ_QSPI_CR_CPHA_MASK         BIT(2)  /* Clock phase */
+#define ZYNQ_QSPI_CR_CPOL_MASK         BIT(1)  /* Clock polarity */
+#define ZYNQ_QSPI_CR_MSTREN_MASK       BIT(0)  /* Mode select */
+#define ZYNQ_QSPI_IXR_RXNEMPTY_MASK    BIT(4)  /* RX_FIFO_not_empty */
+#define ZYNQ_QSPI_IXR_TXOW_MASK                BIT(2)  /* TX_FIFO_not_full */
+#define ZYNQ_QSPI_IXR_ALL_MASK         GENMASK(6, 0)   /* All IXR bits */
+#define ZYNQ_QSPI_ENR_SPI_EN_MASK      BIT(0)  /* SPI Enable */
+#define ZYNQ_QSPI_LQSPICFG_LQMODE_MASK BIT(31) /* Linear QSPI Mode */
 
 /* zynq qspi Transmit Data Register */
 #define ZYNQ_QSPI_TXD_00_00_OFFSET     0x1C    /* Transmit 4-byte inst */
@@ -68,6 +69,9 @@ struct zynq_qspi_regs {
        u32 txd1r;      /* 0x80 */
        u32 txd2r;      /* 0x84 */
        u32 txd3r;      /* 0x88 */
+       u32 reserved1[5];
+       u32 lqspicfg;   /* 0xA0 */
+       u32 lqspists;   /* 0xA4 */
 };
 
 /* zynq qspi platform data */
@@ -97,7 +101,7 @@ static int zynq_qspi_ofdata_to_platdata(struct udevice *bus)
 {
        struct zynq_qspi_platdata *plat = bus->platdata;
        const void *blob = gd->fdt_blob;
-       int node = bus->of_offset;
+       int node = dev_of_offset(bus);
 
        plat->regs = (struct zynq_qspi_regs *)fdtdec_get_addr(blob,
                                                              node, "reg");
@@ -143,6 +147,11 @@ static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv)
                ZYNQ_QSPI_CR_MSTREN_MASK;
        writel(confr, &regs->cr);
 
+       /* Disable the LQSPI feature */
+       confr = readl(&regs->lqspicfg);
+       confr &= ~ZYNQ_QSPI_LQSPICFG_LQMODE_MASK;
+       writel(confr, &regs->lqspicfg);
+
        /* Enable SPI */
        writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr);
 }
@@ -430,7 +439,6 @@ static int zynq_qspi_start_transfer(struct zynq_qspi_priv *priv)
                zynq_qspi_fill_tx_fifo(priv, priv->fifo_depth);
 
        writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->ier);
-       /* Start the transfer by enabling manual start bit */
 
        /* wait for completion */
        do {
@@ -516,7 +524,7 @@ static int zynq_qspi_xfer(struct udevice *dev, unsigned int bitlen,
        priv->rx_buf = din;
        priv->len = bitlen / 8;
 
-       debug("spi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
+       debug("zynq_qspi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
              bus->seq, slave_plat->cs, bitlen, priv->len, flags);
 
        /*
@@ -569,8 +577,7 @@ static int zynq_qspi_set_speed(struct udevice *bus, uint speed)
        writel(confr, &regs->cr);
        priv->freq = speed;
 
-       debug("zynq_spi_set_speed: regs=%p, speed=%d\n",
-             priv->regs, priv->freq);
+       debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
 
        return 0;
 }
@@ -593,7 +600,7 @@ static int zynq_qspi_set_mode(struct udevice *bus, uint mode)
        writel(confr, &regs->cr);
        priv->mode = mode;
 
-       debug("zynq_spi_set_mode: regs=%p, mode=%d\n", priv->regs, priv->mode);
+       debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
 
        return 0;
 }