ddr: altera: stratix10: Add DDR support for Stratix10 SoC

[u-boot] / drivers / spi / zynq_spi.c

diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c
index 2b77f1ccdcf6f16e10b9ee16061cd5400b4acbce..2a02942d413ec751db5cb14367fd7c155fc5cf87 100644 (file)
--- a/drivers/spi/zynq_spi.c
+++ b/drivers/spi/zynq_spi.c
@@ -1,10 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2013 Xilinx, Inc.
  * (C) Copyright 2015 Jagan Teki <jteki@openedev.com>
  *
  * Xilinx Zynq PS SPI controller driver (master mode only)
- *
- * SPDX-License-Identifier:     GPL-2.0+
  */
 
 #include <common.h>
@@ -76,7 +75,7 @@ static int zynq_spi_ofdata_to_platdata(struct udevice *bus)
        const void *blob = gd->fdt_blob;
        int node = dev_of_offset(bus);
 
-       plat->regs = (struct zynq_spi_regs *)dev_get_addr(bus);
+       plat->regs = (struct zynq_spi_regs *)devfdt_get_addr(bus);
 
        /* FIXME: Use 250MHz as a suitable default */
        plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",