net: designware: Add reset ctrl to driver

[u-boot] / drivers / timer / tsc_timer.c

diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c
index 9296de65432dce7c13d01d8189d284d47b84d682..747f190d3845a60fac6d1e1e5d90071525d9b028 100644 (file)
--- a/drivers/timer/tsc_timer.c
+++ b/drivers/timer/tsc_timer.c
@@ -1,10 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (c) 2012 The Chromium OS Authors.
  *
  * TSC calibration codes are adapted from Linux kernel
  * arch/x86/kernel/tsc_msr.c and arch/x86/kernel/tsc.c
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -22,6 +21,17 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static unsigned long cpu_mhz_from_cpuid(void)
+{
+       if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
+               return 0;
+
+       if (cpuid_eax(0) < 0x16)
+               return 0;
+
+       return cpuid_eax(0x16);
+}
+
 /*
  * According to Intel 64 and IA-32 System Programming Guide,
  * if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
@@ -344,13 +354,21 @@ static void tsc_timer_ensure_setup(void)
        if (!gd->arch.clock_rate) {
                unsigned long fast_calibrate;
 
+               fast_calibrate = cpu_mhz_from_cpuid();
+               if (fast_calibrate)
+                       goto done;
+
                fast_calibrate = cpu_mhz_from_msr();
-               if (!fast_calibrate) {
-                       fast_calibrate = quick_pit_calibrate();
-                       if (!fast_calibrate)
-                               panic("TSC frequency is ZERO");
-               }
+               if (fast_calibrate)
+                       goto done;
+
+               fast_calibrate = quick_pit_calibrate();
+               if (fast_calibrate)
+                       goto done;
 
+               panic("TSC frequency is ZERO");
+
+done:
                gd->arch.clock_rate = fast_calibrate * 1000000;
        }
 }
@@ -359,14 +377,23 @@ static int tsc_timer_probe(struct udevice *dev)
 {
        struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
 
-       tsc_timer_ensure_setup();
-       uc_priv->clock_rate = gd->arch.clock_rate;
+       if (!uc_priv->clock_rate) {
+               tsc_timer_ensure_setup();
+               uc_priv->clock_rate = gd->arch.clock_rate;
+       } else {
+               gd->arch.tsc_base = rdtsc();
+       }
 
        return 0;
 }
 
 unsigned long notrace timer_early_get_rate(void)
 {
+       /*
+        * When TSC timer is used as the early timer, be warned that the timer
+        * clock rate can only be calibrated via some hardware ways. Specifying
+        * it in the device tree won't work for the early timer.
+        */
        tsc_timer_ensure_setup();
 
        return gd->arch.clock_rate;