#include <config.h>
#include <mpc85xx.h>
+#include <mpc86xx.h>
#include <common.h>
#include <malloc.h>
#include <net.h>
#if defined(CONFIG_TSEC_ENET)
#include "tsec.h"
+#include "miiphy.h"
-#define TX_BUF_CNT 2
+DECLARE_GLOBAL_DATA_PTR;
+
+#define TX_BUF_CNT 2
static uint rxIdx; /* index of the current RX buffer */
static uint txIdx; /* index of the current TX buffer */
/* The tsec_info structure contains 3 values which the
* driver uses to determine how to operate a given ethernet
- * device. For now, the structure is initialized with the
- * knowledge that all current implementations have 2 TSEC
- * devices, and one FEC. The information needed is:
+ * device. The information needed is:
* phyaddr - The address of the PHY which is attached to
* the given device.
*
*
* phyregidx - This variable specifies which ethernet device
* controls the MII Management registers which are connected
- * to the PHY. For 8540/8560, only TSEC1 (index 0) has
+ * to the PHY. For now, only TSEC1 (index 0) has
* access to the PHYs, so all of the entries have "0".
*
* The values specified in the table are taken from the board's
* config file in include/configs/. When implementing a new
* board with ethernet capability, it is necessary to define:
- * TSEC1_PHY_ADDR
- * TSEC1_PHYIDX
- * TSEC2_PHY_ADDR
- * TSEC2_PHYIDX
+ * TSECn_PHY_ADDR
+ * TSECn_PHYIDX
*
- * and for 8560:
+ * for n = 1,2,3, etc. And for FEC:
* FEC_PHY_ADDR
* FEC_PHYIDX
*/
static struct tsec_info_struct tsec_info[] = {
#if defined(CONFIG_MPC85XX_TSEC1) || defined(CONFIG_MPC83XX_TSEC1)
{TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX},
+#elif defined(CONFIG_MPC86XX_TSEC1)
+ {TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX},
#else
{ 0, 0, 0},
#endif
#if defined(CONFIG_MPC85XX_TSEC2) || defined(CONFIG_MPC83XX_TSEC2)
{TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX},
+#elif defined(CONFIG_MPC86XX_TSEC2)
+ {TSEC2_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC2_PHYIDX},
#else
{ 0, 0, 0},
#endif
#ifdef CONFIG_MPC85XX_FEC
{FEC_PHY_ADDR, 0, FEC_PHYIDX},
#else
-# if defined(CONFIG_MPC85XX_TSEC3) || defined(CONFIG_MPC83XX_TSEC3)
+#if defined(CONFIG_MPC85XX_TSEC3) || defined(CONFIG_MPC83XX_TSEC3) || defined(CONFIG_MPC86XX_TSEC3)
{TSEC3_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC3_PHYIDX},
-# else
+#else
{ 0, 0, 0},
-# endif
-# if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4)
- {TSEC4_PHY_ADDR, TSEC_REDUCED, TSEC4_PHYIDX},
-# else
+#endif
+#if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4) || defined(CONFIG_MPC86XX_TSEC4)
+ {TSEC4_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC4_PHYIDX},
+#else
{ 0, 0, 0},
-# endif
+#endif
#endif
};
void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd);
static void adjust_link(struct eth_device *dev);
static void relocate_cmds(void);
+static int tsec_miiphy_write(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value);
+static int tsec_miiphy_read(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short *value);
/* Initialize device structure. Returns success if PHY
* initialization succeeded (i.e. if it recognizes the PHY)
priv->regs->maccfg1 |= MACCFG1_SOFT_RESET;
priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET);
+#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) \
+ && !defined(BITBANGMII)
+ miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write);
+#endif
+
/* Try to initialize PHY here, and return */
return init_phy(dev);
}
for(i=0;i<MAC_ADDR_LEN;i++) {
tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i];
}
- (uint)(regs->macstnaddr1) = *((uint *)(tmpbuf));
+ regs->macstnaddr1 = *((uint *)(tmpbuf));
tempval = *((uint *)(tmpbuf +4));
- (uint)(regs->macstnaddr2) = tempval;
+ regs->macstnaddr2 = tempval;
/* reset the indices to zero */
rxIdx = 0;
* auto-negotiation */
uint mii_parse_sr(uint mii_reg, struct tsec_private *priv)
{
- uint timeout = TSEC_TIMEOUT;
-
- if(mii_reg & MIIM_STATUS_LINK)
- priv->link = 1;
- else
- priv->link = 0;
+ /*
+ * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
+ */
+ mii_reg = read_phy_reg(priv, MIIM_STATUS);
+ if ((mii_reg & PHY_BMSR_AUTN_ABLE) && !(mii_reg & PHY_BMSR_AUTN_COMP)) {
+ int i = 0;
+
+ puts ("Waiting for PHY auto negotiation to complete");
+ while (!((mii_reg & PHY_BMSR_AUTN_COMP) && (mii_reg & MIIM_STATUS_LINK))) {
+ /*
+ * Timeout reached ?
+ */
+ if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
+ puts (" TIMEOUT !\n");
+ priv->link = 0;
+ return 0;
+ }
- if(priv->link) {
- while((!(mii_reg & MIIM_STATUS_AN_DONE)) && timeout--)
+ if ((i++ % 1000) == 0) {
+ putc ('.');
+ }
+ udelay (1000); /* 1 ms */
mii_reg = read_phy_reg(priv, MIIM_STATUS);
+ }
+ puts (" done\n");
+ priv->link = 1;
+ udelay (500000); /* another 500 ms (results in faster booting) */
+ } else {
+ priv->link = 1;
}
return 0;
{
uint speed;
+ mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
+
+ if (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) &&
+ (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) {
+ int i = 0;
+
+ puts ("Waiting for PHY realtime link");
+ while (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) &&
+ (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) {
+ /*
+ * Timeout reached ?
+ */
+ if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
+ puts (" TIMEOUT !\n");
+ priv->link = 0;
+ break;
+ }
+
+ if ((i++ % 1000) == 0) {
+ putc ('.');
+ }
+ udelay (1000); /* 1 ms */
+ mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
+ }
+ puts (" done\n");
+ udelay (500000); /* another 500 ms (results in faster booting) */
+ }
+
if(mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX)
priv->duplexity = 1;
else
return 0;
}
+/* Parse the vsc8244's status register for speed and duplex
+ * information */
+uint mii_parse_vsc8244(uint mii_reg, struct tsec_private *priv)
+{
+ uint speed;
+
+ if(mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX)
+ priv->duplexity = 1;
+ else
+ priv->duplexity = 0;
+
+ speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED;
+ switch(speed) {
+ case MIIM_VSC8244_AUXCONSTAT_GBIT:
+ priv->speed = 1000;
+ break;
+ case MIIM_VSC8244_AUXCONSTAT_100:
+ priv->speed = 100;
+ break;
+ default:
+ priv->speed = 10;
+ break;
+ }
+
+ return 0;
+}
/* Parse the DM9161's status register for speed and duplex
regs->maccfg2 = ((regs->maccfg2&~(MACCFG2_IF))
| MACCFG2_MII);
- /* If We're in reduced mode, we
- * need to say whether we're 10
- * or 100 MB. */
- if ((priv->speed == 100)
- && (priv->flags & TSEC_REDUCED))
+ /* If We're in reduced mode, we need
+ * to say whether we're 10 or 100 MB.
+ */
+ if ((priv->speed == 100)
+ && (priv->flags & TSEC_REDUCED))
regs->ecntrl |= ECNTRL_R100;
else
regs->ecntrl &= ~(ECNTRL_R100);
},
};
+static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv)
+{
+ unsigned int temp;
+ uint mii_data = read_phy_reg(priv, mii_reg);
+
+
+ /* Setting MIIM_88E1145_PHY_EXT_CR */
+ if (priv->flags & TSEC_REDUCED)
+ return mii_data |
+ MIIM_M88E1145_RGMII_RX_DELAY |
+ MIIM_M88E1145_RGMII_TX_DELAY;
+ else
+ return mii_data;
+}
+
+static struct phy_info phy_info_M88E1145 = {
+ 0x01410cd,
+ "Marvell 88E1145",
+ 4,
+ (struct phy_cmd[]) { /* config */
+ /* Errata E0, E1 */
+ {29, 0x001b, NULL},
+ {30, 0x418f, NULL},
+ {29, 0x0016, NULL},
+ {30, 0xa2da, NULL},
+
+ /* Reset and configure the PHY */
+ {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
+ {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
+ {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
+ {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO, NULL},
+ {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode},
+ {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
+ {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL},
+ {miim_end,}
+ },
+ (struct phy_cmd[]) { /* startup */
+ /* Status is read once to clear old link state */
+ {MIIM_STATUS, miim_read, NULL},
+ /* Auto-negotiate */
+ {MIIM_STATUS, miim_read, &mii_parse_sr},
+ {MIIM_88E1111_PHY_LED_CONTROL, MIIM_88E1111_PHY_LED_DIRECT, NULL},
+ /* Read the Status */
+ {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
+ {miim_end,}
+ },
+ (struct phy_cmd[]) { /* shutdown */
+ {miim_end,}
+ },
+};
+
+
struct phy_info phy_info_cis8204 = {
0x3f11,
"Cicada Cis8204",
{miim_end,}
},
};
+struct phy_info phy_info_VSC8244 = {
+ 0x3f1b,
+ "Vitesse VSC8244",
+ 6,
+ (struct phy_cmd[]) { /* config */
+ /* Override PHY config settings */
+ /* Configure some basic stuff */
+ {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
+ {miim_end,}
+ },
+ (struct phy_cmd[]) { /* startup */
+ /* Read the Status (2x to make sure link is right) */
+ {MIIM_STATUS, miim_read, NULL},
+ /* Auto-negotiate */
+ {MIIM_STATUS, miim_read, &mii_parse_sr},
+ /* Read the status */
+ {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244},
+ {miim_end,}
+ },
+ (struct phy_cmd[]) { /* shutdown */
+ {miim_end,}
+ },
+};
struct phy_info phy_info_dm9161 = {
},
};
+/* Parse the DP83865's link and auto-neg status register for speed and duplex
+ * information */
+uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv)
+{
+ switch (mii_reg & MIIM_DP83865_SPD_MASK) {
+
+ case MIIM_DP83865_SPD_1000:
+ priv->speed = 1000;
+ break;
+
+ case MIIM_DP83865_SPD_100:
+ priv->speed = 100;
+ break;
+
+ default:
+ priv->speed = 10;
+ break;
+
+ }
+
+ if (mii_reg & MIIM_DP83865_DPX_FULL)
+ priv->duplexity = 1;
+ else
+ priv->duplexity = 0;
+
+ return 0;
+}
+
+struct phy_info phy_info_dp83865 = {
+ 0x20005c7,
+ "NatSemi DP83865",
+ 4,
+ (struct phy_cmd[]) { /* config */
+ {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL},
+ {miim_end,}
+ },
+ (struct phy_cmd[]) { /* startup */
+ /* Status is read once to clear old link state */
+ {MIIM_STATUS, miim_read, NULL},
+ /* Auto-negotiate */
+ {MIIM_STATUS, miim_read, &mii_parse_sr},
+ /* Read the link and auto-neg status */
+ {MIIM_DP83865_LANR, miim_read, &mii_parse_dp83865_lanr},
+ {miim_end,}
+ },
+ (struct phy_cmd[]) { /* shutdown */
+ {miim_end,}
+ },
+};
+
struct phy_info *phy_info[] = {
#if 0
&phy_info_cis8201,
&phy_info_cis8204,
&phy_info_M88E1011S,
&phy_info_M88E1111S,
+ &phy_info_M88E1145,
&phy_info_dm9161,
&phy_info_lxt971,
+ &phy_info_VSC8244,
+ &phy_info_dp83865,
NULL
};
printf("%s: PHY id %x is not supported!\n", dev->name, phy_ID);
return NULL;
} else {
- printf("%s: PHY is %s (%x)\n", dev->name, theInfo->name,
- phy_ID);
+ debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID);
}
return theInfo;
struct phy_cmd **cmdlistptr;
struct phy_cmd *cmd;
int i,j,k;
- DECLARE_GLOBAL_DATA_PTR;
for(i=0; phy_info[i]; i++) {
/* First thing's first: relocate the pointers to the
}
-#ifndef CONFIG_BITBANGMII
+#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) \
+ && !defined(BITBANGMII)
struct tsec_private * get_priv_for_phy(unsigned char phyaddr)
{
* Returns:
* 0 on success
*/
-int miiphy_read(unsigned char addr, unsigned char reg, unsigned short *value)
+static int tsec_miiphy_read(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short *value)
{
unsigned short ret;
struct tsec_private *priv = get_priv_for_phy(addr);
* Returns:
* 0 on success
*/
-int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value)
+static int tsec_miiphy_write(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value)
{
struct tsec_private *priv = get_priv_for_phy(addr);
return 0;
}
-#endif /* CONFIG_BITBANGMII */
+#endif /* defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
+ && !defined(BITBANGMII) */
#endif /* CONFIG_TSEC_ENET */
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