/*
* drivers/usb/gadget/dwc2_udc_otg.c
- * Samsung S3C on-chip full/high speed USB OTG 2.0 device controllers
+ * Designware DWC2 on-chip full/high speed USB OTG 2.0 device controllers
*
* Copyright (C) 2008 for Samsung Electronics
*
*/
#undef DEBUG
#include <common.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <linux/list.h>
#include <malloc.h>
#define DEBUG_OUT_EP 0
#define DEBUG_IN_EP 0
-#include <usb/s3c_udc.h>
+#include <usb/dwc2_udc.h>
#define EP0_CON 0
#define EP_MASK 0xF
"WAIT_FOR_NULL_COMPLETE",
};
-#define DRIVER_DESC "DWC2 HS USB OTG Device Driver, (c) Samsung Electronics"
#define DRIVER_VERSION "15 March 2009"
struct dwc2_udc *the_controller;
static const char driver_name[] = "dwc2-udc";
-static const char driver_desc[] = DRIVER_DESC;
static const char ep0name[] = "ep0-control";
/* Max packet size*/
int i;
unsigned int uTemp = writel(CORE_SOFT_RESET, ®->grstctl);
uint32_t dflt_gusbcfg;
+ uint32_t rx_fifo_sz, tx_fifo_sz, np_tx_fifo_sz;
debug("Reseting OTG controller\n");
|0<<7 /* Ulpi DDR sel*/
|0<<6 /* 0: high speed utmi+, 1: full speed serial*/
|0<<4 /* 0: utmi+, 1:ulpi*/
+#ifdef CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8
+ |0<<3 /* phy i/f 0:8bit, 1:16bit*/
+#else
|1<<3 /* phy i/f 0:8bit, 1:16bit*/
+#endif
|0x7<<0; /* HS/FS Timeout**/
if (dev->pdata->usb_gusbcfg)
/* 10. Unmask device IN EP common interrupts*/
writel(DIEPMSK_INIT, ®->diepmsk);
+ rx_fifo_sz = RX_FIFO_SIZE;
+ np_tx_fifo_sz = NPTX_FIFO_SIZE;
+ tx_fifo_sz = PTX_FIFO_SIZE;
+
+ if (dev->pdata->rx_fifo_sz)
+ rx_fifo_sz = dev->pdata->rx_fifo_sz;
+ if (dev->pdata->np_tx_fifo_sz)
+ np_tx_fifo_sz = dev->pdata->np_tx_fifo_sz;
+ if (dev->pdata->tx_fifo_sz)
+ tx_fifo_sz = dev->pdata->tx_fifo_sz;
+
/* 11. Set Rx FIFO Size (in 32-bit words) */
- writel(RX_FIFO_SIZE >> 2, ®->grxfsiz);
+ writel(rx_fifo_sz, ®->grxfsiz);
/* 12. Set Non Periodic Tx FIFO Size */
- writel((NPTX_FIFO_SIZE >> 2) << 16 | ((RX_FIFO_SIZE >> 2)) << 0,
+ writel((np_tx_fifo_sz << 16) | rx_fifo_sz,
®->gnptxfsiz);
for (i = 1; i < DWC2_MAX_HW_ENDPOINTS; i++)
- writel((PTX_FIFO_SIZE >> 2) << 16 |
- ((RX_FIFO_SIZE + NPTX_FIFO_SIZE +
- PTX_FIFO_SIZE*(i-1)) >> 2) << 0,
- ®->dieptxf[i-1]);
+ writel((rx_fifo_sz + np_tx_fifo_sz + tx_fifo_sz*(i-1)) |
+ tx_fifo_sz << 16, ®->dieptxf[i-1]);
/* Flush the RX FIFO */
writel(RX_FIFO_FLUSH, ®->grstctl);
}
/* hardware _could_ do smaller, but driver doesn't */
- if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
- && le16_to_cpu(get_unaligned(&desc->wMaxPacketSize)) !=
+ if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK &&
+ le16_to_cpu(get_unaligned(&desc->wMaxPacketSize)) >
ep_maxpacket(ep)) || !get_unaligned(&desc->wMaxPacketSize)) {
debug("%s: bad %s maxpacket\n", __func__, _ep->name);
* probe - binds to the platform device
*/
-int s3c_udc_probe(struct s3c_plat_otg_data *pdata)
+int dwc2_udc_probe(struct dwc2_plat_otg_data *pdata)
{
struct dwc2_udc *dev = &memory;
int retval = 0;
ROUND(sizeof(struct usb_ctrlrequest),
CONFIG_SYS_CACHELINE_SIZE));
if (!usb_ctrl) {
- error("No memory available for UDC!\n");
+ pr_err("No memory available for UDC!\n");
return -ENOMEM;
}