usb: gadget: g_dnl: hold maximum string descriptor

[u-boot] / drivers / usb / gadget / fotg210.c

diff --git a/drivers/usb/gadget/fotg210.c b/drivers/usb/gadget/fotg210.c
index 6e19db15fafeca32818d4be7bfe28fa033c2341b..e061b2e8a65d3fbdacc9c99d7bfb38ed930156ab 100644 (file)
--- a/drivers/usb/gadget/fotg210.c
+++ b/drivers/usb/gadget/fotg210.c
@@ -13,7 +13,7 @@
 #include <net.h>
 #include <malloc.h>
 #include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <linux/types.h>
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
@@ -245,6 +245,7 @@ static int fotg210_dma(struct fotg210_ep *ep, struct fotg210_request *req)
                if (ep->id == 0) {
                        /* Wait until cx/ep0 fifo empty */
                        fotg210_cxwait(chip, CXFIFO_CXFIFOE);
+                       udelay(1);
                        writel(DMAFIFO_CX, &regs->dma_fifo);
                } else {
                        /* Wait until epx fifo empty */
@@ -831,7 +832,7 @@ static struct fotg210_chip controller = {
        },
 };
 
-int usb_gadget_handle_interrupts(void)
+int usb_gadget_handle_interrupts(int index)
 {
        struct fotg210_chip *chip = &controller;
        struct fotg210_regs *regs = chip->regs;
@@ -847,6 +848,13 @@ int usb_gadget_handle_interrupts(void)
        /* CX interrupts */
        if (gisr & GISR_GRP0) {
                st = readl(&regs->gisr0);
+               /*
+                * Write 1 and then 0 works for both W1C & RW.
+                *
+                * HW v1.11.0+: It's a W1C register (write 1 clear)
+                * HW v1.10.0-: It's a R/W register (write 0 clear)
+                */
+               writel(st & GISR0_CXABORT, &regs->gisr0);
                writel(0, &regs->gisr0);
 
                if (st & GISR0_CXERR)
@@ -873,6 +881,13 @@ int usb_gadget_handle_interrupts(void)
        /* Device Status Interrupts */
        if (gisr & GISR_GRP2) {
                st = readl(&regs->gisr2);
+               /*
+                * Write 1 and then 0 works for both W1C & RW.
+                *
+                * HW v1.11.0+: It's a W1C register (write 1 clear)
+                * HW v1.10.0-: It's a R/W register (write 0 clear)
+                */
+               writel(st, &regs->gisr2);
                writel(0, &regs->gisr2);
 
                if (st & GISR2_RESET)