dm: core: Replace of_offset with accessor

[u-boot] / drivers / usb / host / dwc2.c

diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index b272c571120dff2b99cc69a687002e3f7842b99f..d253b946f334a2fae4cfad5f7a89da60c4433266 100644 (file)
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -13,10 +13,13 @@
 #include <memalign.h>
 #include <phys2bus.h>
 #include <usbroothubdes.h>
+#include <wait_bit.h>
 #include <asm/io.h>
 
 #include "dwc2.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* Use only HC channel 0. */
 #define DWC2_HC_CHANNEL                        0
 
@@ -38,6 +41,8 @@ struct dwc2_priv {
        u8 out_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
        struct dwc2_core_regs *regs;
        int root_hub_devnum;
+       bool ext_vbus;
+       bool oc_disable;
 };
 
 #ifndef CONFIG_DM_USB
@@ -53,27 +58,6 @@ static struct dwc2_priv local;
 /*
  * DWC2 IP interface
  */
-static int wait_for_bit(void *reg, const uint32_t mask, bool set)
-{
-       unsigned int timeout = 1000000;
-       uint32_t val;
-
-       while (--timeout) {
-               val = readl(reg);
-               if (!set)
-                       val = ~val;
-
-               if ((val & mask) == mask)
-                       return 0;
-
-               udelay(1);
-       }
-
-       debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
-             __func__, reg, mask, set);
-
-       return -ETIMEDOUT;
-}
 
 /*
  * Initializes the FSLSPClkSel field of the HCFG register
@@ -118,7 +102,8 @@ static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
 
        writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
               &regs->grstctl);
-       ret = wait_for_bit(&regs->grstctl, DWC2_GRSTCTL_TXFFLSH, 0);
+       ret = wait_for_bit(__func__, &regs->grstctl, DWC2_GRSTCTL_TXFFLSH,
+                          false, 1000, false);
        if (ret)
                printf("%s: Timeout!\n", __func__);
 
@@ -136,7 +121,8 @@ static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs)
        int ret;
 
        writel(DWC2_GRSTCTL_RXFFLSH, &regs->grstctl);
-       ret = wait_for_bit(&regs->grstctl, DWC2_GRSTCTL_RXFFLSH, 0);
+       ret = wait_for_bit(__func__, &regs->grstctl, DWC2_GRSTCTL_RXFFLSH,
+                          false, 1000, false);
        if (ret)
                printf("%s: Timeout!\n", __func__);
 
@@ -153,13 +139,15 @@ static void dwc_otg_core_reset(struct dwc2_core_regs *regs)
        int ret;
 
        /* Wait for AHB master IDLE state. */
-       ret = wait_for_bit(&regs->grstctl, DWC2_GRSTCTL_AHBIDLE, 1);
+       ret = wait_for_bit(__func__, &regs->grstctl, DWC2_GRSTCTL_AHBIDLE,
+                          true, 1000, false);
        if (ret)
                printf("%s: Timeout!\n", __func__);
 
        /* Core Soft Reset */
        writel(DWC2_GRSTCTL_CSFTRST, &regs->grstctl);
-       ret = wait_for_bit(&regs->grstctl, DWC2_GRSTCTL_CSFTRST, 0);
+       ret = wait_for_bit(__func__, &regs->grstctl, DWC2_GRSTCTL_CSFTRST,
+                          false, 1000, false);
        if (ret)
                printf("%s: Timeout!\n", __func__);
 
@@ -244,8 +232,8 @@ static void dwc_otg_core_host_init(struct dwc2_core_regs *regs)
                clrsetbits_le32(&regs->hc_regs[i].hcchar,
                                DWC2_HCCHAR_EPDIR,
                                DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
-               ret = wait_for_bit(&regs->hc_regs[i].hcchar,
-                                  DWC2_HCCHAR_CHEN, 0);
+               ret = wait_for_bit(__func__, &regs->hc_regs[i].hcchar,
+                                  DWC2_HCCHAR_CHEN, false, 1000, false);
                if (ret)
                        printf("%s: Timeout!\n", __func__);
        }
@@ -268,8 +256,9 @@ static void dwc_otg_core_host_init(struct dwc2_core_regs *regs)
  *
  * @param regs Programming view of the DWC_otg controller
  */
-static void dwc_otg_core_init(struct dwc2_core_regs *regs)
+static void dwc_otg_core_init(struct dwc2_priv *priv)
 {
+       struct dwc2_core_regs *regs = priv->regs;
        uint32_t ahbcfg = 0;
        uint32_t usbcfg = 0;
        uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
@@ -278,11 +267,15 @@ static void dwc_otg_core_init(struct dwc2_core_regs *regs)
        usbcfg = readl(&regs->gusbcfg);
 
        /* Program the ULPI External VBUS bit if needed */
-#ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
-       usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
-#else
-       usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
-#endif
+       if (priv->ext_vbus) {
+               usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
+               if (!priv->oc_disable) {
+                       usbcfg |= DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR |
+                                 DWC2_GUSBCFG_INDICATOR_PASSTHROUGH;
+               }
+       } else {
+               usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
+       }
 
        /* Set external TS Dline pulsing */
 #ifdef CONFIG_DWC2_TS_DLINE
@@ -745,7 +738,8 @@ int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, u8 *toggle)
        int ret;
        uint32_t hcint, hctsiz;
 
-       ret = wait_for_bit(&hc_regs->hcint, DWC2_HCINT_CHHLTD, true);
+       ret = wait_for_bit(__func__, &hc_regs->hcint, DWC2_HCINT_CHHLTD, true,
+                          1000, false);
        if (ret)
                return ret;
 
@@ -1069,7 +1063,13 @@ static int dwc2_init_common(struct dwc2_priv *priv)
                return -ENODEV;
        }
 
-       dwc_otg_core_init(regs);
+#ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
+       priv->ext_vbus = 1;
+#else
+       priv->ext_vbus = 0;
+#endif
+
+       dwc_otg_core_init(priv);
        dwc_otg_core_host_init(regs);
 
        clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
@@ -1088,6 +1088,15 @@ static int dwc2_init_common(struct dwc2_priv *priv)
                }
        }
 
+       /*
+        * Add a 1 second delay here. This gives the host controller
+        * a bit time before the comminucation with the USB devices
+        * is started (the bus is scanned) and  fixes the USB detection
+        * problems with some problematic USB keys.
+        */
+       if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
+               mdelay(1000);
+
        return 0;
 }
 
@@ -1182,6 +1191,7 @@ static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev,
 static int dwc2_usb_ofdata_to_platdata(struct udevice *dev)
 {
        struct dwc2_priv *priv = dev_get_priv(dev);
+       const void *prop;
        fdt_addr_t addr;
 
        addr = dev_get_addr(dev);
@@ -1189,12 +1199,20 @@ static int dwc2_usb_ofdata_to_platdata(struct udevice *dev)
                return -EINVAL;
        priv->regs = (struct dwc2_core_regs *)addr;
 
+       prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
+                          "disable-over-current", NULL);
+       if (prop)
+               priv->oc_disable = true;
+
        return 0;
 }
 
 static int dwc2_usb_probe(struct udevice *dev)
 {
        struct dwc2_priv *priv = dev_get_priv(dev);
+       struct usb_bus_priv *bus_priv = dev_get_uclass_priv(dev);
+
+       bus_priv->desc_before_addr = true;
 
        return dwc2_init_common(priv);
 }